Lines Matching refs:f
144 return f"{self.peripheral.name}_{self.name}"
170 print(f"Skipping download of CMSIS Pack for {family}, already exists")
172 print(f"Downloading CMSIS Pack for {family}")
183 print(f"Parsing SVD for {svd_path.stem}")
202 signal = SIGNAL_ALIAS.get(f"{peripheral}::{signal}", signal)
210 signal = SIGNAL_ALIAS.get(f"{peripheral}::{signal}", signal)
220 print(f"Parsing Pin Tool for {pin_tool.parent.stem}")
221 with open(pin_tool, 'r') as f:
222 tree = lxml.etree.parse(f)
229 pt_peripheral = f"PRS.{signal.name}"
235 …for node in tree.getroot().xpath(f'portIo/pinRoutes/module[@name="{pt_peripheral}"]/selector[@name…
236 for loc in node.xpath(f'route[@name="{pt_signal}"]/location'):
245 print(f"WARN: No Pin Tool match for {signal.display_name()} for {pin_tool.parent.stem}")
254 f" * Copyright (c) {datetime.date.today().year} Silicon Laboratories Inc.",
257 f" * Pin Control for Silicon Labs {family.upper()} devices",
259 f" * This file was generated by the script {Path(__file__).name} in the hal_silabs module.",
263 f"#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_{family.upper()}_PINCTRL_H_",
264 f"#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_{family.upper()}_PINCTRL_H_",
276 lines.append(f"#define SILABS_DBUS_{signal.display_name()}(port, pin){' ' * pad}"
277 f"SILABS_DBUS(port, pin, {peripheral.offset}, {int(signal.have_enable)}, "
278 f"{signal.enable}, {signal.route})")
281 print(f"WARN: No route register for {signal.display_name()}")
292 lines.append(f"#define {signal.display_name()}_P{chr(65 + port)}{pin}{' ' * pad}"
293 f"SILABS_DBUS_{signal.display_name()}(0x{port:x}, 0x{pin:x})")
306 …lines.append(f"#define ABUS_{abus["bus_name"]}_{abus["peripheral"]}{' ' * (max_len - curr_len + 1)…
307 … f"SILABS_ABUS(0x{abus["base_offset"]:x}, 0x{abus["parity"]:x}, 0x{abus["value"]:x})")
310 lines.append(f"#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_{family.upper()}_PINCTRL_H_ */")
313 (path / f"{family}-pinctrl.h").write_text("\n".join(lines))
326 with file.open() as f:
327 for line in f: