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Searched refs:_CMU_LFEPRESC0_RTCC_DIV2 (Results 1 – 25 of 80) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_cmu.h1778 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
1781 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_cmu.h1778 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
1781 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_cmu.h1778 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
1781 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_cmu.h1850 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
1853 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_cmu.h1850 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
1853 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p732f512gm32.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p732f512gm48.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p733f512gm48.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p532f512gm48.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p632f512gm32.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p632f512gm48.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p632f512im32.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p632f512im48.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defr32bg13p532f512gm32.h4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_cmu.h2222 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
2225 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defm32gg12b390f1024gl112.h6038 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
6041 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defm32gg12b390f512gl112.h6038 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
6041 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defm32gg12b530f512il120.h6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defm32gg12b530f512im64.h6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defm32gg12b530f512iq100.h6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defm32gg12b530f512iq64.h6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
Defm32gg12b530f512gq100.h6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_cmu.h2289 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode… macro
2292 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shif…
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_cmu.c8295 #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) in CMU_ClockPrescSet()
8296 EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); in CMU_ClockPrescSet()
8448 #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) in CMU_ClockPrescSet()
8449 EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); in CMU_ClockPrescSet()
/hal_silabs-latest/gecko/emlib/src/
Dem_cmu.c8242 #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) in CMU_ClockPrescSet()
8243 EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); in CMU_ClockPrescSet()
8395 #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) in CMU_ClockPrescSet()
8396 EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); in CMU_ClockPrescSet()

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