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Searched refs:_CMU_CTRL_CLKOUTSEL1_HFSRCCLK (Results 1 – 25 of 80) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_cmu.h190 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
204 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_cmu.h190 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
204 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_cmu.h194 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_cmu.h194 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_cmu.h194 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_cmu.h201 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
215 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_cmu.h201 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
215 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p732f512gm32.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p732f512gm48.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p733f512gm48.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p532f512gm48.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p632f512gm32.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p632f512gm48.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p632f512im32.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p632f512im48.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
Defr32bg13p532f512gm32.h2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**… macro
2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_cmu.h201 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
216 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
Defm32gg12b390f1024gl112.h4037 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
4052 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
Defm32gg12b390f512gl112.h4037 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
4052 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
Defm32gg12b530f512il120.h4876 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
4891 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
Defm32gg12b530f512im64.h4876 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
4891 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
Defm32gg12b530f512iq100.h4876 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
4891 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
Defm32gg12b530f512iq64.h4876 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
4891 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
Defm32gg12b530f512gq100.h4876 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
4891 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_cmu.h201 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /*… macro
216 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /*…

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