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Searched refs:SMU_PRIVILEGED_IRQn (Results 1 – 20 of 20) sorted by relevance

/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Dsystem_efr32bg22.h71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn macro
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/
Dsystem_efr32mg29.h71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn macro
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/
Dsystem_efr32bg29.h71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn macro
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/
Dsystem_efr32bg27.h71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn macro
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/
Dsystem_efr32fg23.h71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn macro
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/
Dsystem_efr32mg24.h71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn macro
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/
Dsystem_efr32zg23.h71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn macro
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21a010f512im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21a010f768im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21a020f1024im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21a020f512im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21a020f768im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21b010f1024im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21b010f512im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21b010f768im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21b020f1024im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21b020f512im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Defr32mg21b020f768im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator
Drm21z000f1024im32.h70 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ enumerator