1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // This file applies to the SIM3U1XX_CLKCTRL_A module 24 // 25 // Script: 0.57 26 // Version: 1 27 28 #ifndef __SI32_CLKCTRL_A_REGISTERS_H__ 29 #define __SI32_CLKCTRL_A_REGISTERS_H__ 30 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct SI32_CLKCTRL_A_CONTROL_Struct 38 { 39 union 40 { 41 struct 42 { 43 // AHB Clock Source Select 44 volatile uint32_t AHBSEL: 3; 45 uint32_t reserved0: 5; 46 // AHB Clock Divider 47 volatile uint32_t AHBDIV: 3; 48 uint32_t reserved1: 5; 49 // APB Clock Divider 50 volatile uint32_t APBDIV: 1; 51 uint32_t reserved2: 11; 52 // External Clock Edge Select 53 volatile uint32_t EXTESEL: 1; 54 // Oscillators Busy Flag 55 volatile uint32_t OBUSYF: 1; 56 uint32_t reserved3: 2; 57 }; 58 volatile uint32_t U32; 59 }; 60 }; 61 62 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_MASK 0x00000007 63 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT 0 64 // AHB clock source is the Low-Power Oscillator. 65 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE 0 66 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_U32 \ 67 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 68 // AHB clock source is the Low-Frequency Oscillator. 69 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE 1 70 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_U32 \ 71 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 72 // AHB clock source is the RTC Oscillator. 73 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_VALUE 2 74 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_U32 \ 75 (SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 76 // AHB clock source is the External Oscillator. 77 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE 3 78 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_U32 \ 79 (SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 80 // AHB clock source is the USB Oscillator. 81 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_USB0OSC_VALUE 4 82 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_USB0OSC_U32 \ 83 (SI32_CLKCTRL_A_CONTROL_AHBSEL_USB0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 84 // AHB clock source is the PLL. 85 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE 5 86 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_U32 \ 87 (SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 88 // AHB clock source is a divided version of the Low-Power Oscillator. 89 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE 6 90 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_U32 \ 91 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 92 93 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_MASK 0x00000700 94 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT 8 95 // AHB clock divided by 1. 96 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE 0 97 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_U32 \ 98 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 99 // AHB clock divided by 2. 100 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE 1 101 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_U32 \ 102 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 103 // AHB clock divided by 4. 104 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE 2 105 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_U32 \ 106 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 107 // AHB clock divided by 8. 108 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE 3 109 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_U32 \ 110 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 111 // AHB clock divided by 16. 112 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE 4 113 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_U32 \ 114 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 115 // AHB clock divided by 32. 116 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE 5 117 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_U32 \ 118 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 119 // AHB clock divided by 64. 120 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE 6 121 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_U32 \ 122 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 123 // AHB clock divided by 128. 124 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE 7 125 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_U32 \ 126 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 127 128 #define SI32_CLKCTRL_A_CONTROL_APBDIV_MASK 0x00010000 129 #define SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT 16 130 // APB clock is the same as the AHB clock (divided by 1). 131 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE 0 132 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_U32 \ 133 (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) 134 // APB clock is the AHB clock divided by 2. 135 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE 1 136 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_U32 \ 137 (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) 138 139 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_MASK 0x10000000 140 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT 28 141 // External clock generated by both rising and falling edges of the external 142 // oscillator. 143 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE 0 144 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_U32 \ 145 (SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) 146 // External clock generated by only rising edges of the external oscillator. 147 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE 1 148 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_U32 \ 149 (SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) 150 151 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_MASK 0x20000000 152 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT 29 153 // AHB and APB oscillators are not busy. 154 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE 0 155 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_U32 \ 156 (SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) 157 // AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields 158 // should not be modified. 159 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE 1 160 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_U32 \ 161 (SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) 162 163 164 165 struct SI32_CLKCTRL_A_AHBCLKG_Struct 166 { 167 union 168 { 169 struct 170 { 171 // RAM Clock Enable 172 volatile uint32_t RAMCEN: 1; 173 // DMA Controller Clock Enable 174 volatile uint32_t DMACEN: 1; 175 // Flash Clock Enable 176 volatile uint32_t FLASHCEN: 1; 177 // EMIF Clock Enable 178 volatile uint32_t EMIF0CEN: 1; 179 // USB0 Buffer Clock Enable 180 volatile uint32_t USB0BCEN: 1; 181 uint32_t reserved0: 27; 182 }; 183 volatile uint32_t U32; 184 }; 185 }; 186 187 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_MASK 0x00000001 188 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT 0 189 // Disable the AHB clock to the RAM. 190 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE 0 191 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_U32 \ 192 (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) 193 // Enable the AHB clock to the RAM (default). 194 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE 1 195 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_U32 \ 196 (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) 197 198 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_MASK 0x00000002 199 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT 1 200 // Disable the AHB clock to the DMA Controller (default). 201 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE 0 202 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_U32 \ 203 (SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) 204 // Enable the AHB clock to the DMA Controller. 205 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE 1 206 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_U32 \ 207 (SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) 208 209 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_MASK 0x00000004 210 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT 2 211 // Disable the AHB clock to the Flash. 212 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE 0 213 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_U32 \ 214 (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) 215 // Enable the AHB clock to the Flash (default). 216 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE 1 217 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_U32 \ 218 (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) 219 220 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_MASK 0x00000008 221 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT 3 222 // Disable the AHB clock to the External Memory Interface (EMIF) (default). 223 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_VALUE 0 224 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_U32 \ 225 (SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT) 226 // Enable the AHB clock to the External Memory Interface (EMIF). 227 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_VALUE 1 228 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_U32 \ 229 (SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT) 230 231 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_MASK 0x00000010 232 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_SHIFT 4 233 // Disable the AHB clock to the USB0 Buffer (default). 234 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_DISABLED_VALUE 0 235 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_DISABLED_U32 \ 236 (SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_SHIFT) 237 // Enable the AHB clock to the USB0 Buffer. 238 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_ENABLED_VALUE 1 239 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_ENABLED_U32 \ 240 (SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_SHIFT) 241 242 243 244 struct SI32_CLKCTRL_A_APBCLKG0_Struct 245 { 246 union 247 { 248 struct 249 { 250 // PLL Module Clock Enable 251 volatile uint32_t PLL0CEN: 1; 252 // Port Bank Module Clock Enable 253 volatile uint32_t PB0CEN: 1; 254 // USART0 Module Clock Enable 255 volatile uint32_t USART0CEN: 1; 256 // USART1 Module Clock Enable 257 volatile uint32_t USART1CEN: 1; 258 // UART0 Module Clock Enable 259 volatile uint32_t UART0CEN: 1; 260 // UART1 Module Clock Enable 261 volatile uint32_t UART1CEN: 1; 262 // SPI0 Module Clock Enable 263 volatile uint32_t SPI0CEN: 1; 264 // SPI1 Module Clock Enable 265 volatile uint32_t SPI1CEN: 1; 266 // SPI2 Module Clock Enable 267 volatile uint32_t SPI2CEN: 1; 268 // I2C0 Module Clock Enable 269 volatile uint32_t I2C0CEN: 1; 270 // I2C1 Module Clock Enable 271 volatile uint32_t I2C1CEN: 1; 272 // EPCA0 Module Clock Enable 273 volatile uint32_t EPCA0CEN: 1; 274 // PCA0 Module Clock Enable 275 volatile uint32_t PCA0CEN: 1; 276 // PCA1 Module Clock Enable 277 volatile uint32_t PCA1CEN: 1; 278 // SSG0 Module Clock Enable 279 volatile uint32_t SSG0CEN: 1; 280 // TIMER0 Module Clock Enable 281 volatile uint32_t TIMER0CEN: 1; 282 // TIMER1 Module Clock Enable 283 volatile uint32_t TIMER1CEN: 1; 284 // SARADC0 Module Clock Enable 285 volatile uint32_t ADC0CEN: 1; 286 // SARADC1 Module Clock Enable 287 volatile uint32_t ADC1CEN: 1; 288 // Comparator 0 Module Clock Enable 289 volatile uint32_t CMP0CEN: 1; 290 // Comparator 1 Module Clock Enable 291 volatile uint32_t CMP1CEN: 1; 292 // Capacitive Sensing (CAPSENSE0) Module Clock Enable 293 volatile uint32_t CS0CEN: 1; 294 // AES0 Module Clock Enable 295 volatile uint32_t AES0CEN: 1; 296 // CRC0 Module Clock Enable 297 volatile uint32_t CRC0CEN: 1; 298 // IDAC0 Module Clock Enable 299 volatile uint32_t IDAC0CEN: 1; 300 // IDAC1 Module Clock Enable 301 volatile uint32_t IDAC1CEN: 1; 302 // Low Power Timer (LPTIMER0) Module Clock Enable 303 volatile uint32_t LPT0CEN: 1; 304 // I2S0 Module Clock Enable 305 volatile uint32_t I2S0CEN: 1; 306 // USB0 Module Clock Enable 307 volatile uint32_t USB0CEN: 1; 308 // External Regulator Clock Enable 309 volatile uint32_t EVREGCEN: 1; 310 // Flash Controller Clock Enable 311 volatile uint32_t FLCTRLCEN: 1; 312 uint32_t reserved0: 1; 313 }; 314 volatile uint32_t U32; 315 }; 316 }; 317 318 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_MASK 0x00000001 319 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT 0 320 // Disable the APB clock to the PLL0 registers (default). 321 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE 0 322 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_U32 \ 323 (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) 324 // Enable the APB clock to the PLL0 registers. 325 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE 1 326 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_U32 \ 327 (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) 328 329 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_MASK 0x00000002 330 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT 1 331 // Disable the APB clock to the Port Bank Modules (default). 332 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE 0 333 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_U32 \ 334 (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) 335 // Enable the APB clock to the Port Bank Modules. 336 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE 1 337 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_U32 \ 338 (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) 339 340 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_MASK 0x00000004 341 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT 2 342 // Disable the APB clock to the USART0 Module (default). 343 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE 0 344 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_U32 \ 345 (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) 346 // Enable the APB clock to the USART0 Module. 347 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE 1 348 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_U32 \ 349 (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) 350 351 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_MASK 0x00000008 352 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT 3 353 // Disable the APB clock to the USART1 Module (default). 354 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_VALUE 0 355 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_U32 \ 356 (SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT) 357 // Enable the APB clock to the USART1 Module. 358 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_VALUE 1 359 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_U32 \ 360 (SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT) 361 362 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_MASK 0x00000010 363 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT 4 364 // Disable the APB clock to the UART0 Module (default). 365 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE 0 366 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_U32 \ 367 (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) 368 // Enable the APB clock to the UART0 Module. 369 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE 1 370 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_U32 \ 371 (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) 372 373 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_MASK 0x00000020 374 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT 5 375 // Disable the APB clock to the UART1 Module (default). 376 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_VALUE 0 377 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_U32 \ 378 (SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT) 379 // Enable the APB clock to the UART1 Module. 380 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_VALUE 1 381 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_U32 \ 382 (SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT) 383 384 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_MASK 0x00000040 385 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT 6 386 // Disable the APB clock to the SPI0 Module (default). 387 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE 0 388 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_U32 \ 389 (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) 390 // Enable the APB clock to the SPI0 Module. 391 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE 1 392 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_U32 \ 393 (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) 394 395 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_MASK 0x00000080 396 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT 7 397 // Disable the APB clock to the SPI1 Module (default). 398 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE 0 399 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_U32 \ 400 (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) 401 // Enable the APB clock to the SPI1 Module. 402 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE 1 403 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_U32 \ 404 (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) 405 406 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_MASK 0x00000100 407 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT 8 408 // Disable the APB clock to the SPI2 Module (default). 409 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_VALUE 0 410 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_U32 \ 411 (SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT) 412 // Enable the APB clock to the SPI2 Module. 413 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_VALUE 1 414 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_U32 \ 415 (SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT) 416 417 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_MASK 0x00000200 418 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT 9 419 // Disable the APB clock to the I2C0 Module (default). 420 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE 0 421 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_U32 \ 422 (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) 423 // Enable the APB clock to the I2C0 Module. 424 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE 1 425 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_U32 \ 426 (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) 427 428 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_MASK 0x00000400 429 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT 10 430 // Disable the APB clock to the I2C1 Module (default). 431 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_VALUE 0 432 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_U32 \ 433 (SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT) 434 // Enable the APB clock to the I2C1 Module. 435 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_VALUE 1 436 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_U32 \ 437 (SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT) 438 439 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_MASK 0x00000800 440 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT 11 441 // Disable the APB clock to the EPCA0 Module (default). 442 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE 0 443 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_U32 \ 444 (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) 445 // Enable the APB clock to the EPCA0 Module. 446 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE 1 447 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_U32 \ 448 (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) 449 450 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_MASK 0x00001000 451 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT 12 452 // Disable the APB clock to the PCA0 Module (default). 453 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_VALUE 0 454 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_U32 \ 455 (SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT) 456 // Enable the APB clock to the PCA0 Module. 457 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_VALUE 1 458 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_U32 \ 459 (SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT) 460 461 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_MASK 0x00002000 462 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT 13 463 // Disable the APB clock to the PCA1 Module (default). 464 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_VALUE 0 465 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_U32 \ 466 (SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT) 467 // Enable the APB clock to the PCA1 Module. 468 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_VALUE 1 469 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_U32 \ 470 (SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT) 471 472 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_MASK 0x00004000 473 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT 14 474 // Disable the APB clock to the SSG0 Module (default). 475 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_VALUE 0 476 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_U32 \ 477 (SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT) 478 // Enable the APB clock to the SSG0 Module. 479 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_VALUE 1 480 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_U32 \ 481 (SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT) 482 483 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_MASK 0x00008000 484 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT 15 485 // Disable the APB clock to the TIMER0 Module (default). 486 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE 0 487 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_U32 \ 488 (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) 489 // Enable the APB clock to the TIMER0 Module. 490 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE 1 491 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_U32 \ 492 (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) 493 494 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_MASK 0x00010000 495 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT 16 496 // Disable the APB clock to the TIMER1 Module (default). 497 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE 0 498 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_U32 \ 499 (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) 500 // Enable the APB clock to the TIMER1 Module. 501 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE 1 502 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_U32 \ 503 (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) 504 505 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_MASK 0x00020000 506 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT 17 507 // Disable the APB clock to the SARADC0 Module (default). 508 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE 0 509 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_U32 \ 510 (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) 511 // Enable the APB clock to the SARADC0 Module. 512 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE 1 513 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_U32 \ 514 (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) 515 516 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_MASK 0x00040000 517 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT 18 518 // Disable the APB clock to the SARADC1 Module (default). 519 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_VALUE 0 520 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_U32 \ 521 (SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT) 522 // Enable the APB clock to the SARADC1 Module. 523 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_VALUE 1 524 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_U32 \ 525 (SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT) 526 527 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_MASK 0x00080000 528 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT 19 529 // Disable the APB clock to the Comparator 0 Module (default). 530 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE 0 531 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_U32 \ 532 (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) 533 // Enable the APB clock to the Comparator 0 Module. 534 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE 1 535 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_U32 \ 536 (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) 537 538 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_MASK 0x00100000 539 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT 20 540 // Disable the APB clock to the Comparator 1 Module (default). 541 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE 0 542 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_U32 \ 543 (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) 544 // Enable the APB clock to the Comparator 1 Module. 545 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE 1 546 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_U32 \ 547 (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) 548 549 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_MASK 0x00200000 550 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT 21 551 // Disable the APB clock to the CAPSENSE0 Module (default). 552 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_VALUE 0 553 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_U32 \ 554 (SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT) 555 // Enable the APB clock to the CAPSENSE0 Module. 556 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_VALUE 1 557 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_U32 \ 558 (SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT) 559 560 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_MASK 0x00400000 561 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT 22 562 // Disable the APB clock to the AES0 Module (default). 563 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE 0 564 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_U32 \ 565 (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) 566 // Enable the APB clock to the AES0 Module. 567 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE 1 568 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_U32 \ 569 (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) 570 571 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_MASK 0x00800000 572 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT 23 573 // Disable the APB clock to the CRC0 Module (default). 574 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE 0 575 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_U32 \ 576 (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) 577 // Enable the APB clock to the CRC0 Module. 578 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE 1 579 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_U32 \ 580 (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) 581 582 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_MASK 0x01000000 583 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT 24 584 // Disable the APB clock to the IDAC0 Module (default). 585 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE 0 586 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_U32 \ 587 (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) 588 // Enable the APB clock to the IDAC0 Module. 589 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE 1 590 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_U32 \ 591 (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) 592 593 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_MASK 0x02000000 594 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT 25 595 // Disable the APB clock to the IDAC1 Module (default). 596 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_VALUE 0 597 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_U32 \ 598 (SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT) 599 // Enable the APB clock to the IDAC1 Module. 600 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_VALUE 1 601 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_U32 \ 602 (SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT) 603 604 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_MASK 0x04000000 605 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT 26 606 // Disable the APB clock to the LPTIMER0 Module (default). 607 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE 0 608 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_U32 \ 609 (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) 610 // Enable the APB clock to the LPTIMER0 Module. 611 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE 1 612 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_U32 \ 613 (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) 614 615 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_MASK 0x08000000 616 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT 27 617 // Disable the APB clock to the I2S0 Module (default). 618 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_VALUE 0 619 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_U32 \ 620 (SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT) 621 // Enable the APB clock to the I2S0 Module. 622 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_VALUE 1 623 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_U32 \ 624 (SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT) 625 626 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_MASK 0x10000000 627 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_SHIFT 28 628 // Disable the APB clock to the USB0 Module (default). 629 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_DISABLED_VALUE 0 630 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_DISABLED_U32 \ 631 (SI32_CLKCTRL_A_APBCLKG0_USB0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USB0CEN_SHIFT) 632 // Enable the APB clock to the USB0 Module. 633 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_ENABLED_VALUE 1 634 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_ENABLED_U32 \ 635 (SI32_CLKCTRL_A_APBCLKG0_USB0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USB0CEN_SHIFT) 636 637 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_MASK 0x20000000 638 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT 29 639 // Disable the APB clock to the External Regulator Module (EXTVREG0) (default). 640 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_VALUE 0 641 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_U32 \ 642 (SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT) 643 // Enable the APB clock to the External Regulator Module (EXTVREG0). 644 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_VALUE 1 645 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_U32 \ 646 (SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT) 647 648 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_MASK 0x40000000 649 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT 30 650 // Disable the APB clock to the Flash Controller Module (FLASHCTRL0) (default). 651 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE 0 652 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_U32 \ 653 (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) 654 // Enable the APB clock to the Flash Controller Module (FLASHCTRL0). 655 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE 1 656 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_U32 \ 657 (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) 658 659 660 661 struct SI32_CLKCTRL_A_APBCLKG1_Struct 662 { 663 union 664 { 665 struct 666 { 667 // Miscellaneous 0 Clock Enable 668 volatile uint32_t MISC0CEN: 1; 669 // Miscellaneous 1 Clock Enable 670 volatile uint32_t MISC1CEN: 1; 671 // Miscellaneous 2 Clock Enable 672 volatile uint32_t MISC2CEN: 1; 673 uint32_t reserved0: 29; 674 }; 675 volatile uint32_t U32; 676 }; 677 }; 678 679 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_MASK 0x00000001 680 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT 0 681 // Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, 682 // LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default). 683 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE 0 684 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_U32 \ 685 (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) 686 // Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, 687 // LPOSC0, EXTVREG0, IVC0 and RTC0 modules. 688 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE 1 689 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_U32 \ 690 (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) 691 692 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_MASK 0x00000002 693 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT 1 694 // Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar 695 // (DMAXBAR0) modules. 696 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE 0 697 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_U32 \ 698 (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) 699 // Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar 700 // (DMAXBAR0) modules (default). 701 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE 1 702 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_U32 \ 703 (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) 704 705 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_MASK 0x00000004 706 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT 2 707 // Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default). 708 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_VALUE 0 709 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_U32 \ 710 (SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT) 711 // Enable the APB clock to the OSCVLDF flag in the EXTOSC module. 712 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_VALUE 1 713 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_U32 \ 714 (SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT) 715 716 717 718 struct SI32_CLKCTRL_A_PM3CN_Struct 719 { 720 union 721 { 722 struct 723 { 724 // Power Mode 3 Fast-Wake Clock Source 725 volatile uint32_t PM3CSEL: 3; 726 uint32_t reserved0: 13; 727 // Power Mode 3 Fast-Wake Clock Enable 728 volatile uint32_t PM3CEN: 1; 729 uint32_t reserved1: 15; 730 }; 731 volatile uint32_t U32; 732 }; 733 }; 734 735 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_MASK 0x00000007 736 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT 0 737 // Power Mode 3 clock source is the Low-Power Oscillator. 738 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE 0 739 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_U32 \ 740 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 741 // Power Mode 3 clock source is the Low-Frequency Oscillator. 742 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE 1 743 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_U32 \ 744 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 745 // Power Mode 3 clock source is the RTC Oscillator. 746 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_VALUE 2 747 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_U32 \ 748 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 749 // Power Mode 3 clock source is the External Oscillator. 750 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE 3 751 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_U32 \ 752 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 753 // Power Mode 3 clock source is the USB Oscillator. 754 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_USB0OSC_VALUE 4 755 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_USB0OSC_U32 \ 756 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_USB0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 757 // Power Mode 3 clock source is the PLL. 758 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE 5 759 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_U32 \ 760 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 761 // Power Mode 3 clock source is a divided version of the Low-Power Oscillator. 762 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE 6 763 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_U32 \ 764 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 765 766 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_MASK 0x00010000 767 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT 16 768 // Disable the core clock when in Power Mode 3. 769 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE 0 770 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_U32 \ 771 (SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) 772 // The core clock is enabled and runs off the clock selected by PM3CSEL in Power 773 // Mode 3. 774 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE 1 775 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_U32 \ 776 (SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) 777 778 779 780 typedef struct SI32_CLKCTRL_A_Struct 781 { 782 struct SI32_CLKCTRL_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 783 uint32_t reserved0; 784 uint32_t reserved1; 785 uint32_t reserved2; 786 struct SI32_CLKCTRL_A_AHBCLKG_Struct AHBCLKG ; // Base Address + 0x10 787 volatile uint32_t AHBCLKG_SET; 788 volatile uint32_t AHBCLKG_CLR; 789 uint32_t reserved3; 790 struct SI32_CLKCTRL_A_APBCLKG0_Struct APBCLKG0 ; // Base Address + 0x20 791 volatile uint32_t APBCLKG0_SET; 792 volatile uint32_t APBCLKG0_CLR; 793 uint32_t reserved4; 794 struct SI32_CLKCTRL_A_APBCLKG1_Struct APBCLKG1 ; // Base Address + 0x30 795 volatile uint32_t APBCLKG1_SET; 796 volatile uint32_t APBCLKG1_CLR; 797 uint32_t reserved5; 798 struct SI32_CLKCTRL_A_PM3CN_Struct PM3CN ; // Base Address + 0x40 799 uint32_t reserved6; 800 uint32_t reserved7; 801 uint32_t reserved8; 802 } SI32_CLKCTRL_A_Type; 803 804 #ifdef __cplusplus 805 } 806 #endif 807 808 #endif // __SI32_CLKCTRL_A_REGISTERS_H__ 809 810 //-eof-------------------------------------------------------------------------- 811 812
