//------------------------------------------------------------------------------ // Copyright 2012 (c) Silicon Laboratories Inc. // // SPDX-License-Identifier: Zlib // // This siHAL software is provided 'as-is', without any express or implied // warranty. In no event will the authors be held liable for any damages // arising from the use of this software. // // Permission is granted to anyone to use this software for any purpose, // including commercial applications, and to alter it and redistribute it // freely, subject to the following restrictions: // // 1. The origin of this software must not be misrepresented; you must not // claim that you wrote the original software. If you use this software // in a product, an acknowledgment in the product documentation would be // appreciated but is not required. // 2. Altered source versions must be plainly marked as such, and must not be // misrepresented as being the original software. // 3. This notice may not be removed or altered from any source distribution. //------------------------------------------------------------------------------ // // This file applies to the SIM3U1XX_CLKCTRL_A module // // Script: 0.57 // Version: 1 #ifndef __SI32_CLKCTRL_A_REGISTERS_H__ #define __SI32_CLKCTRL_A_REGISTERS_H__ #include #ifdef __cplusplus extern "C" { #endif struct SI32_CLKCTRL_A_CONTROL_Struct { union { struct { // AHB Clock Source Select volatile uint32_t AHBSEL: 3; uint32_t reserved0: 5; // AHB Clock Divider volatile uint32_t AHBDIV: 3; uint32_t reserved1: 5; // APB Clock Divider volatile uint32_t APBDIV: 1; uint32_t reserved2: 11; // External Clock Edge Select volatile uint32_t EXTESEL: 1; // Oscillators Busy Flag volatile uint32_t OBUSYF: 1; uint32_t reserved3: 2; }; volatile uint32_t U32; }; }; #define SI32_CLKCTRL_A_CONTROL_AHBSEL_MASK 0x00000007 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT 0 // AHB clock source is the Low-Power Oscillator. #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE 0 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) // AHB clock source is the Low-Frequency Oscillator. #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE 1 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) // AHB clock source is the RTC Oscillator. #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_VALUE 2 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) // AHB clock source is the External Oscillator. #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE 3 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) // AHB clock source is the USB Oscillator. #define SI32_CLKCTRL_A_CONTROL_AHBSEL_USB0OSC_VALUE 4 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_USB0OSC_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBSEL_USB0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) // AHB clock source is the PLL. #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE 5 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) // AHB clock source is a divided version of the Low-Power Oscillator. #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE 6 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) #define SI32_CLKCTRL_A_CONTROL_AHBDIV_MASK 0x00000700 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT 8 // AHB clock divided by 1. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE 0 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) // AHB clock divided by 2. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE 1 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) // AHB clock divided by 4. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE 2 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) // AHB clock divided by 8. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE 3 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) // AHB clock divided by 16. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE 4 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) // AHB clock divided by 32. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE 5 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) // AHB clock divided by 64. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE 6 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) // AHB clock divided by 128. #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE 7 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_U32 \ (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) #define SI32_CLKCTRL_A_CONTROL_APBDIV_MASK 0x00010000 #define SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT 16 // APB clock is the same as the AHB clock (divided by 1). #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE 0 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_U32 \ (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) // APB clock is the AHB clock divided by 2. #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE 1 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_U32 \ (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) #define SI32_CLKCTRL_A_CONTROL_EXTESEL_MASK 0x10000000 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT 28 // External clock generated by both rising and falling edges of the external // oscillator. #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE 0 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_U32 \ (SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) // External clock generated by only rising edges of the external oscillator. #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE 1 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_U32 \ (SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) #define SI32_CLKCTRL_A_CONTROL_OBUSYF_MASK 0x20000000 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT 29 // AHB and APB oscillators are not busy. #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE 0 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_U32 \ (SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) // AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields // should not be modified. #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE 1 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_U32 \ (SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) struct SI32_CLKCTRL_A_AHBCLKG_Struct { union { struct { // RAM Clock Enable volatile uint32_t RAMCEN: 1; // DMA Controller Clock Enable volatile uint32_t DMACEN: 1; // Flash Clock Enable volatile uint32_t FLASHCEN: 1; // EMIF Clock Enable volatile uint32_t EMIF0CEN: 1; // USB0 Buffer Clock Enable volatile uint32_t USB0BCEN: 1; uint32_t reserved0: 27; }; volatile uint32_t U32; }; }; #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_MASK 0x00000001 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT 0 // Disable the AHB clock to the RAM. #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) // Enable the AHB clock to the RAM (default). #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_MASK 0x00000002 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT 1 // Disable the AHB clock to the DMA Controller (default). #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) // Enable the AHB clock to the DMA Controller. #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_MASK 0x00000004 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT 2 // Disable the AHB clock to the Flash. #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) // Enable the AHB clock to the Flash (default). #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_MASK 0x00000008 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT 3 // Disable the AHB clock to the External Memory Interface (EMIF) (default). #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT) // Enable the AHB clock to the External Memory Interface (EMIF). #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_EMIF0CEN_SHIFT) #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_MASK 0x00000010 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_SHIFT 4 // Disable the AHB clock to the USB0 Buffer (default). #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_DISABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_SHIFT) // Enable the AHB clock to the USB0 Buffer. #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_ENABLED_U32 \ (SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_USB0BCEN_SHIFT) struct SI32_CLKCTRL_A_APBCLKG0_Struct { union { struct { // PLL Module Clock Enable volatile uint32_t PLL0CEN: 1; // Port Bank Module Clock Enable volatile uint32_t PB0CEN: 1; // USART0 Module Clock Enable volatile uint32_t USART0CEN: 1; // USART1 Module Clock Enable volatile uint32_t USART1CEN: 1; // UART0 Module Clock Enable volatile uint32_t UART0CEN: 1; // UART1 Module Clock Enable volatile uint32_t UART1CEN: 1; // SPI0 Module Clock Enable volatile uint32_t SPI0CEN: 1; // SPI1 Module Clock Enable volatile uint32_t SPI1CEN: 1; // SPI2 Module Clock Enable volatile uint32_t SPI2CEN: 1; // I2C0 Module Clock Enable volatile uint32_t I2C0CEN: 1; // I2C1 Module Clock Enable volatile uint32_t I2C1CEN: 1; // EPCA0 Module Clock Enable volatile uint32_t EPCA0CEN: 1; // PCA0 Module Clock Enable volatile uint32_t PCA0CEN: 1; // PCA1 Module Clock Enable volatile uint32_t PCA1CEN: 1; // SSG0 Module Clock Enable volatile uint32_t SSG0CEN: 1; // TIMER0 Module Clock Enable volatile uint32_t TIMER0CEN: 1; // TIMER1 Module Clock Enable volatile uint32_t TIMER1CEN: 1; // SARADC0 Module Clock Enable volatile uint32_t ADC0CEN: 1; // SARADC1 Module Clock Enable volatile uint32_t ADC1CEN: 1; // Comparator 0 Module Clock Enable volatile uint32_t CMP0CEN: 1; // Comparator 1 Module Clock Enable volatile uint32_t CMP1CEN: 1; // Capacitive Sensing (CAPSENSE0) Module Clock Enable volatile uint32_t CS0CEN: 1; // AES0 Module Clock Enable volatile uint32_t AES0CEN: 1; // CRC0 Module Clock Enable volatile uint32_t CRC0CEN: 1; // IDAC0 Module Clock Enable volatile uint32_t IDAC0CEN: 1; // IDAC1 Module Clock Enable volatile uint32_t IDAC1CEN: 1; // Low Power Timer (LPTIMER0) Module Clock Enable volatile uint32_t LPT0CEN: 1; // I2S0 Module Clock Enable volatile uint32_t I2S0CEN: 1; // USB0 Module Clock Enable volatile uint32_t USB0CEN: 1; // External Regulator Clock Enable volatile uint32_t EVREGCEN: 1; // Flash Controller Clock Enable volatile uint32_t FLCTRLCEN: 1; uint32_t reserved0: 1; }; volatile uint32_t U32; }; }; #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_MASK 0x00000001 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT 0 // Disable the APB clock to the PLL0 registers (default). #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) // Enable the APB clock to the PLL0 registers. #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_MASK 0x00000002 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT 1 // Disable the APB clock to the Port Bank Modules (default). #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) // Enable the APB clock to the Port Bank Modules. #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_MASK 0x00000004 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT 2 // Disable the APB clock to the USART0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) // Enable the APB clock to the USART0 Module. #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_MASK 0x00000008 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT 3 // Disable the APB clock to the USART1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_USART1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT) // Enable the APB clock to the USART1 Module. #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_USART1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_MASK 0x00000010 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT 4 // Disable the APB clock to the UART0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) // Enable the APB clock to the UART0 Module. #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_MASK 0x00000020 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT 5 // Disable the APB clock to the UART1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_UART1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT) // Enable the APB clock to the UART1 Module. #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_UART1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_MASK 0x00000040 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT 6 // Disable the APB clock to the SPI0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) // Enable the APB clock to the SPI0 Module. #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_MASK 0x00000080 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT 7 // Disable the APB clock to the SPI1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) // Enable the APB clock to the SPI1 Module. #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_MASK 0x00000100 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT 8 // Disable the APB clock to the SPI2 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT) // Enable the APB clock to the SPI2 Module. #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI2CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_MASK 0x00000200 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT 9 // Disable the APB clock to the I2C0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) // Enable the APB clock to the I2C0 Module. #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_MASK 0x00000400 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT 10 // Disable the APB clock to the I2C1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT) // Enable the APB clock to the I2C1 Module. #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_MASK 0x00000800 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT 11 // Disable the APB clock to the EPCA0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) // Enable the APB clock to the EPCA0 Module. #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_MASK 0x00001000 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT 12 // Disable the APB clock to the PCA0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT) // Enable the APB clock to the PCA0 Module. #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_MASK 0x00002000 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT 13 // Disable the APB clock to the PCA1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT) // Enable the APB clock to the PCA1 Module. #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PCA1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_MASK 0x00004000 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT 14 // Disable the APB clock to the SSG0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT) // Enable the APB clock to the SSG0 Module. #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SSG0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_MASK 0x00008000 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT 15 // Disable the APB clock to the TIMER0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) // Enable the APB clock to the TIMER0 Module. #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_MASK 0x00010000 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT 16 // Disable the APB clock to the TIMER1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) // Enable the APB clock to the TIMER1 Module. #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_MASK 0x00020000 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT 17 // Disable the APB clock to the SARADC0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) // Enable the APB clock to the SARADC0 Module. #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_MASK 0x00040000 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT 18 // Disable the APB clock to the SARADC1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT) // Enable the APB clock to the SARADC1 Module. #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_MASK 0x00080000 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT 19 // Disable the APB clock to the Comparator 0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) // Enable the APB clock to the Comparator 0 Module. #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_MASK 0x00100000 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT 20 // Disable the APB clock to the Comparator 1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) // Enable the APB clock to the Comparator 1 Module. #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_MASK 0x00200000 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT 21 // Disable the APB clock to the CAPSENSE0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CS0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT) // Enable the APB clock to the CAPSENSE0 Module. #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CS0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CS0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_MASK 0x00400000 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT 22 // Disable the APB clock to the AES0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) // Enable the APB clock to the AES0 Module. #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_MASK 0x00800000 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT 23 // Disable the APB clock to the CRC0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) // Enable the APB clock to the CRC0 Module. #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_MASK 0x01000000 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT 24 // Disable the APB clock to the IDAC0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) // Enable the APB clock to the IDAC0 Module. #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_MASK 0x02000000 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT 25 // Disable the APB clock to the IDAC1 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT) // Enable the APB clock to the IDAC1 Module. #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_MASK 0x04000000 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT 26 // Disable the APB clock to the LPTIMER0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) // Enable the APB clock to the LPTIMER0 Module. #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_MASK 0x08000000 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT 27 // Disable the APB clock to the I2S0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT) // Enable the APB clock to the I2S0 Module. #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2S0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_MASK 0x10000000 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_SHIFT 28 // Disable the APB clock to the USB0 Module (default). #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_USB0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USB0CEN_SHIFT) // Enable the APB clock to the USB0 Module. #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_USB0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_USB0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USB0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_MASK 0x20000000 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT 29 // Disable the APB clock to the External Regulator Module (EXTVREG0) (default). #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT) // Enable the APB clock to the External Regulator Module (EXTVREG0). #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EVREGCEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_MASK 0x40000000 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT 30 // Disable the APB clock to the Flash Controller Module (FLASHCTRL0) (default). #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) // Enable the APB clock to the Flash Controller Module (FLASHCTRL0). #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) struct SI32_CLKCTRL_A_APBCLKG1_Struct { union { struct { // Miscellaneous 0 Clock Enable volatile uint32_t MISC0CEN: 1; // Miscellaneous 1 Clock Enable volatile uint32_t MISC1CEN: 1; // Miscellaneous 2 Clock Enable volatile uint32_t MISC2CEN: 1; uint32_t reserved0: 29; }; volatile uint32_t U32; }; }; #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_MASK 0x00000001 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT 0 // Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, // LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default). #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) // Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, // LPOSC0, EXTVREG0, IVC0 and RTC0 modules. #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_MASK 0x00000002 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT 1 // Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar // (DMAXBAR0) modules. #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) // Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar // (DMAXBAR0) modules (default). #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_MASK 0x00000004 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT 2 // Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default). #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT) // Enable the APB clock to the OSCVLDF flag in the EXTOSC module. #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC2CEN_SHIFT) struct SI32_CLKCTRL_A_PM3CN_Struct { union { struct { // Power Mode 3 Fast-Wake Clock Source volatile uint32_t PM3CSEL: 3; uint32_t reserved0: 13; // Power Mode 3 Fast-Wake Clock Enable volatile uint32_t PM3CEN: 1; uint32_t reserved1: 15; }; volatile uint32_t U32; }; }; #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_MASK 0x00000007 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT 0 // Power Mode 3 clock source is the Low-Power Oscillator. #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE 0 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) // Power Mode 3 clock source is the Low-Frequency Oscillator. #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE 1 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) // Power Mode 3 clock source is the RTC Oscillator. #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_VALUE 2 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) // Power Mode 3 clock source is the External Oscillator. #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE 3 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) // Power Mode 3 clock source is the USB Oscillator. #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_USB0OSC_VALUE 4 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_USB0OSC_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CSEL_USB0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) // Power Mode 3 clock source is the PLL. #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE 5 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) // Power Mode 3 clock source is a divided version of the Low-Power Oscillator. #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE 6 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) #define SI32_CLKCTRL_A_PM3CN_PM3CEN_MASK 0x00010000 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT 16 // Disable the core clock when in Power Mode 3. #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE 0 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) // The core clock is enabled and runs off the clock selected by PM3CSEL in Power // Mode 3. #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE 1 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_U32 \ (SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) typedef struct SI32_CLKCTRL_A_Struct { struct SI32_CLKCTRL_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 uint32_t reserved0; uint32_t reserved1; uint32_t reserved2; struct SI32_CLKCTRL_A_AHBCLKG_Struct AHBCLKG ; // Base Address + 0x10 volatile uint32_t AHBCLKG_SET; volatile uint32_t AHBCLKG_CLR; uint32_t reserved3; struct SI32_CLKCTRL_A_APBCLKG0_Struct APBCLKG0 ; // Base Address + 0x20 volatile uint32_t APBCLKG0_SET; volatile uint32_t APBCLKG0_CLR; uint32_t reserved4; struct SI32_CLKCTRL_A_APBCLKG1_Struct APBCLKG1 ; // Base Address + 0x30 volatile uint32_t APBCLKG1_SET; volatile uint32_t APBCLKG1_CLR; uint32_t reserved5; struct SI32_CLKCTRL_A_PM3CN_Struct PM3CN ; // Base Address + 0x40 uint32_t reserved6; uint32_t reserved7; uint32_t reserved8; } SI32_CLKCTRL_A_Type; #ifdef __cplusplus } #endif #endif // __SI32_CLKCTRL_A_REGISTERS_H__ //-eof--------------------------------------------------------------------------