| /hal_silabs-latest/gecko/emlib/src/ |
| D | em_rtc.c | 83 if (RTC->FREEZE & RTC_FREEZE_REGFREEZE) { in regSync()
89 while (RTC->SYNCBUSY & mask) in regSync()
118 ret = RTC->COMP[comp].COMP; in RTC_CompareGet()
123 ret = RTC->COMP0; in RTC_CompareGet()
127 ret = RTC->COMP1; in RTC_CompareGet()
173 compReg = &(RTC->COMP[comp].COMP); in RTC_CompareSet()
178 compReg = &(RTC->COMP0); in RTC_CompareSet()
185 compReg = &(RTC->COMP1); in RTC_CompareSet()
227 BUS_RegBitWrite(&(RTC->CTRL), _RTC_CTRL_EN_SHIFT, enable); in RTC_Enable()
275 while (RTC->SYNCBUSY) in RTC_FreezeEnable()
[all …]
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| /hal_silabs-latest/simplicity_sdk/platform/emlib/src/ |
| D | em_rtc.c | 83 if (RTC->FREEZE & RTC_FREEZE_REGFREEZE) { in regSync()
89 while (RTC->SYNCBUSY & mask) in regSync()
118 ret = RTC->COMP[comp].COMP; in RTC_CompareGet()
123 ret = RTC->COMP0; in RTC_CompareGet()
127 ret = RTC->COMP1; in RTC_CompareGet()
173 compReg = &(RTC->COMP[comp].COMP); in RTC_CompareSet()
178 compReg = &(RTC->COMP0); in RTC_CompareSet()
185 compReg = &(RTC->COMP1); in RTC_CompareSet()
227 BUS_RegBitWrite(&(RTC->CTRL), _RTC_CTRL_EN_SHIFT, enable); in RTC_Enable()
275 while (RTC->SYNCBUSY) in RTC_FreezeEnable()
[all …]
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| /hal_silabs-latest/gecko/emlib/inc/ |
| D | em_rtc.h | 95 return RTC->CNT; in RTC_CounterGet()
108 RTC->CNT = value; in RTC_CounterSet()
130 RTC->IFC = flags; in RTC_IntClear()
144 RTC->IEN &= ~flags; in RTC_IntDisable()
163 RTC->IEN |= flags; in RTC_IntEnable()
179 return RTC->IF; in RTC_IntGet()
200 ien = RTC->IEN; in RTC_IntGetEnabled()
201 return RTC->IF & ien; in RTC_IntGetEnabled()
215 RTC->IFS = flags; in RTC_IntSet()
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| /hal_silabs-latest/gecko/Device/SiliconLabs/EFM32HG/Include/ |
| D | efm32hg309f32.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32hg309f64.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32hg310f32.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32hg310f64.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32hg322f32.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32hg322f64.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32hg350f32.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32hg350f64.h | 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| /hal_silabs-latest/gecko/Device/SiliconLabs/EFM32WG/Include/ |
| D | efm32wg980f64.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg990f128.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg990f256.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg990f64.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg995f128.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg900f256.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg980f128.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg980f256.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg995f256.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg995f64.h | 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg380f128.h | 453 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg380f256.h | 453 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| D | efm32wg380f64.h | 453 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ macro
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| /hal_silabs-latest/simplicity_sdk/platform/service/sleeptimer/src/ |
| D | sl_sleeptimer_hal_prortc.c | 80 #warning A value other than 1 for SL_SLEEPTIMER_FREQ_DIVIDER is not supported on Radio Internal RTC…
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