Searched refs:MODE_CLR (Results 1 – 18 of 18) sorted by relevance
211 basePointer->MODE_CLR = SI32_CMP_A_MODE_NMUX_MASK; in _SI32_CMP_A_select_negative_input()228 basePointer->MODE_CLR = SI32_CMP_A_MODE_PMUX_MASK; in _SI32_CMP_A_select_positive_input()252 basePointer->MODE_CLR = SI32_CMP_A_MODE_INMUX_MASK; in _SI32_CMP_A_select_mux()270 basePointer->MODE_CLR = SI32_CMP_A_MODE_CMPMD_MASK; in _SI32_CMP_A_select_response_power_mode()297 basePointer->MODE_CLR = SI32_CMP_A_MODE_FIEN_MASK; in _SI32_CMP_A_disable_falling_edge_interrupt()336 basePointer->MODE_CLR = SI32_CMP_A_MODE_RIEN_MASK; in _SI32_CMP_A_disable_rising_edge_interrupt()366 basePointer->MODE_CLR = SI32_CMP_A_MODE_DACLVL_MASK; in _SI32_CMP_A_write_dac_level_setting()408 basePointer->MODE_CLR = SI32_CMP_A_MODE_NWPUEN_MASK; in _SI32_CMP_A_disable_negative_weak_pullup()434 basePointer->MODE_CLR = SI32_CMP_A_MODE_PWPUEN_MASK; in _SI32_CMP_A_disable_positive_weak_pullup()447 basePointer->MODE_CLR = SI32_CMP_A_MODE_CMPHYN_MASK; in _SI32_CMP_A_select_negative_hysteresis_disabled()[all …]
260 basePointer->MODE_CLR = SI32_CMP_A_MODE_NMUX_MASK;\282 basePointer->MODE_CLR = SI32_CMP_A_MODE_PMUX_MASK;\311 basePointer->MODE_CLR = SI32_CMP_A_MODE_INMUX_MASK;\334 basePointer->MODE_CLR = SI32_CMP_A_MODE_CMPMD_MASK;\362 (basePointer->MODE_CLR = SI32_CMP_A_MODE_FIEN_MASK)401 (basePointer->MODE_CLR = SI32_CMP_A_MODE_RIEN_MASK)437 basePointer->MODE_CLR = SI32_CMP_A_MODE_DACLVL_MASK;\482 (basePointer->MODE_CLR = SI32_CMP_A_MODE_NWPUEN_MASK)508 (basePointer->MODE_CLR = SI32_CMP_A_MODE_PWPUEN_MASK)521 (basePointer->MODE_CLR = SI32_CMP_A_MODE_CMPHYN_MASK)[all …]
617 basePointer->MODE_CLR = SI32_USART_B_MODE_DBGMD_MASK; in _SI32_USART_B_disable_stall_in_debug_mode()630 basePointer->MODE_CLR = SI32_USART_B_MODE_LBMD_MASK; in _SI32_USART_B_exit_loopback_mode()643 basePointer->MODE_CLR = SI32_USART_B_MODE_LBMD_MASK; in _SI32_USART_B_enter_receive_loopback_mode()657 basePointer->MODE_CLR = SI32_USART_B_MODE_LBMD_MASK; in _SI32_USART_B_enter_transmit_loopback_mode()697 basePointer->MODE_CLR = SI32_USART_B_MODE_STPSTCLK_MASK; in _SI32_USART_B_disable_master_generate_clock_during_stop()723 basePointer->MODE_CLR = SI32_USART_B_MODE_STRTSTCLK_MASK; in _SI32_USART_B_disable_master_generate_clock_during_start()749 basePointer->MODE_CLR = SI32_USART_B_MODE_ISTCLK_MASK; in _SI32_USART_B_disable_master_generate_clock_between_transfers()775 basePointer->MODE_CLR = SI32_USART_B_MODE_DUPLEXMD_MASK; in _SI32_USART_B_enter_full_duplex_mode()788 basePointer->MODE_CLR = SI32_USART_B_MODE_CLKIDLE_MASK; in _SI32_USART_B_select_sync_clock_low_during_idle()814 basePointer->MODE_CLR = SI32_USART_B_MODE_CLKESEL_MASK; in _SI32_USART_B_select_clock_edge_falling()[all …]
616 basePointer->MODE_CLR = SI32_USART_A_MODE_DBGMD_MASK; in _SI32_USART_A_disable_stall_in_debug_mode()629 basePointer->MODE_CLR = SI32_USART_A_MODE_LBMD_MASK; in _SI32_USART_A_exit_loopback_mode()642 basePointer->MODE_CLR = SI32_USART_A_MODE_LBMD_MASK; in _SI32_USART_A_enter_receive_loopback_mode()656 basePointer->MODE_CLR = SI32_USART_A_MODE_LBMD_MASK; in _SI32_USART_A_enter_transmit_loopback_mode()696 basePointer->MODE_CLR = SI32_USART_A_MODE_STPSTCLK_MASK; in _SI32_USART_A_disable_master_generate_clock_during_stop()722 basePointer->MODE_CLR = SI32_USART_A_MODE_STRTSTCLK_MASK; in _SI32_USART_A_disable_master_generate_clock_during_start()748 basePointer->MODE_CLR = SI32_USART_A_MODE_ISTCLK_MASK; in _SI32_USART_A_disable_master_generate_clock_between_transfers()774 basePointer->MODE_CLR = SI32_USART_A_MODE_DUPLEXMD_MASK; in _SI32_USART_A_enter_full_duplex_mode()787 basePointer->MODE_CLR = SI32_USART_A_MODE_CLKIDLE_MASK; in _SI32_USART_A_select_sync_clock_low_during_idle()813 basePointer->MODE_CLR = SI32_USART_A_MODE_CLKESEL_MASK; in _SI32_USART_A_select_clock_edge_falling()[all …]
516 basePointer->MODE_CLR = SI32_UART_B_MODE_RTCCKMD_MASK; in _SI32_UART_B_select_apb_clock_mode()542 basePointer->MODE_CLR = SI32_UART_B_MODE_RTCBDMD_MASK; in _SI32_UART_B_exit_rtc_baud_rate_mode()555 basePointer->MODE_CLR = SI32_UART_B_MODE_FORCECLK_MASK; in _SI32_UART_B_select_internal_clock_on_demand()607 basePointer->MODE_CLR = SI32_UART_B_MODE_RXCLKSW_MASK; in _SI32_UART_B_disable_rx_clock_switch()633 basePointer->MODE_CLR = SI32_UART_B_MODE_TXCLKSW_MASK; in _SI32_UART_B_disable_tx_clock_switch()659 basePointer->MODE_CLR = SI32_UART_B_MODE_DBGMD_MASK; in _SI32_UART_B_disable_stall_in_debug_mode()672 basePointer->MODE_CLR = SI32_UART_B_MODE_LBMD_MASK; in _SI32_UART_B_exit_loopback_mode()685 basePointer->MODE_CLR = SI32_UART_B_MODE_LBMD_MASK; in _SI32_UART_B_enter_receive_loopback_mode()699 basePointer->MODE_CLR = SI32_UART_B_MODE_LBMD_MASK; in _SI32_UART_B_enter_transmit_loopback_mode()739 basePointer->MODE_CLR = SI32_UART_B_MODE_DUPLEXMD_MASK; in _SI32_UART_B_enter_full_duplex_mode()[all …]
717 (basePointer->MODE_CLR = SI32_USART_A_MODE_DBGMD_MASK)730 (basePointer->MODE_CLR = SI32_USART_A_MODE_LBMD_MASK)743 basePointer->MODE_CLR = SI32_USART_A_MODE_LBMD_MASK;\758 basePointer->MODE_CLR = SI32_USART_A_MODE_LBMD_MASK;\799 (basePointer->MODE_CLR = SI32_USART_A_MODE_STPSTCLK_MASK)825 (basePointer->MODE_CLR = SI32_USART_A_MODE_STRTSTCLK_MASK)851 (basePointer->MODE_CLR = SI32_USART_A_MODE_ISTCLK_MASK)877 (basePointer->MODE_CLR = SI32_USART_A_MODE_DUPLEXMD_MASK)890 (basePointer->MODE_CLR = SI32_USART_A_MODE_CLKIDLE_MASK)916 (basePointer->MODE_CLR = SI32_USART_A_MODE_CLKESEL_MASK)[all …]
717 (basePointer->MODE_CLR = SI32_USART_B_MODE_DBGMD_MASK)730 (basePointer->MODE_CLR = SI32_USART_B_MODE_LBMD_MASK)743 basePointer->MODE_CLR = SI32_USART_B_MODE_LBMD_MASK;\758 basePointer->MODE_CLR = SI32_USART_B_MODE_LBMD_MASK;\799 (basePointer->MODE_CLR = SI32_USART_B_MODE_STPSTCLK_MASK)825 (basePointer->MODE_CLR = SI32_USART_B_MODE_STRTSTCLK_MASK)851 (basePointer->MODE_CLR = SI32_USART_B_MODE_ISTCLK_MASK)877 (basePointer->MODE_CLR = SI32_USART_B_MODE_DUPLEXMD_MASK)890 (basePointer->MODE_CLR = SI32_USART_B_MODE_CLKIDLE_MASK)916 (basePointer->MODE_CLR = SI32_USART_B_MODE_CLKESEL_MASK)[all …]
621 (basePointer->MODE_CLR = SI32_UART_B_MODE_RTCCKMD_MASK)647 (basePointer->MODE_CLR = SI32_UART_B_MODE_RTCBDMD_MASK)660 (basePointer->MODE_CLR = SI32_UART_B_MODE_FORCECLK_MASK)712 (basePointer->MODE_CLR = SI32_UART_B_MODE_RXCLKSW_MASK)738 (basePointer->MODE_CLR = SI32_UART_B_MODE_TXCLKSW_MASK)764 (basePointer->MODE_CLR = SI32_UART_B_MODE_DBGMD_MASK)777 (basePointer->MODE_CLR = SI32_UART_B_MODE_LBMD_MASK)790 basePointer->MODE_CLR = SI32_UART_B_MODE_LBMD_MASK;\805 basePointer->MODE_CLR = SI32_UART_B_MODE_LBMD_MASK;\846 (basePointer->MODE_CLR = SI32_UART_B_MODE_DUPLEXMD_MASK)[all …]
591 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_CGSEL_MASK; in _SI32_CAPSENSE_A_set_gain()612 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_RAMPSEL_MASK; in _SI32_CAPSENSE_A_set_ramp_selection()632 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_IASEL_MASK; in _SI32_CAPSENSE_A_set_output_current()651 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_DTSEL_MASK; in _SI32_CAPSENSE_A_set_discharge_time()
702 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_CGSEL_MASK;\730 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_RAMPSEL_MASK;\757 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_IASEL_MASK;\783 basePointer->MODE_CLR = SI32_CAPSENSE_A_MODE_DTSEL_MASK;\
564 basePointer->MODE_CLR = SI32_UART_A_MODE_DBGMD_MASK; in _SI32_UART_A_disable_stall_in_debug_mode()577 basePointer->MODE_CLR = SI32_UART_A_MODE_LBMD_MASK; in _SI32_UART_A_exit_loopback_mode()590 basePointer->MODE_CLR = SI32_UART_A_MODE_LBMD_MASK; in _SI32_UART_A_enter_receive_loopback_mode()604 basePointer->MODE_CLR = SI32_UART_A_MODE_LBMD_MASK; in _SI32_UART_A_enter_transmit_loopback_mode()644 basePointer->MODE_CLR = SI32_UART_A_MODE_DUPLEXMD_MASK; in _SI32_UART_A_enter_full_duplex_mode()670 basePointer->MODE_CLR = SI32_UART_A_MODE_ITSEN_MASK; in _SI32_UART_A_disable_idle_tx_tristate()
665 (basePointer->MODE_CLR = SI32_UART_A_MODE_DBGMD_MASK)678 (basePointer->MODE_CLR = SI32_UART_A_MODE_LBMD_MASK)691 basePointer->MODE_CLR = SI32_UART_A_MODE_LBMD_MASK;\706 basePointer->MODE_CLR = SI32_UART_A_MODE_LBMD_MASK;\747 (basePointer->MODE_CLR = SI32_UART_A_MODE_DUPLEXMD_MASK)773 (basePointer->MODE_CLR = SI32_UART_A_MODE_ITSEN_MASK)
421 volatile uint32_t MODE_CLR; member
579 volatile uint32_t MODE_CLR; member
1155 volatile uint32_t MODE_CLR; member
1167 volatile uint32_t MODE_CLR; member
1329 volatile uint32_t MODE_CLR; member
1346 volatile uint32_t MODE_CLR; member
