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Searched refs:DPLL0 (Results 1 – 25 of 116) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/service/power_manager/src/sleep_loop/
Dsl_power_manager_hal_s2.c200 is_dpll_used = ((DPLL0->STATUS & _DPLL_STATUS_ENS_MASK) != 0); in sli_power_manager_init_hardware()
253 …li_power_manager_convert_delay_us_to_tick(DPLL_LOCKING_DELAY_US_FUNCTION((DPLL0->CFG1 & _DPLL_CFG1… in sli_power_manager_init_hardware()
343 DPLL0->EN_CLR = DPLL_EN_EN; in SL_CODE_CLASSIFY()
344 while ((DPLL0->EN & _DPLL_EN_DISABLING_MASK) != 0) { in SL_CODE_CLASSIFY()
519 DPLL0->EN_SET = DPLL_EN_EN; in sli_power_manager_restore_states()
520 while ((DPLL0->STATUS & _DPLL_STATUS_RDY_MASK) == 0U) { in sli_power_manager_restore_states()
/hal_silabs-latest/gecko/emlib/src/
Dem_emu.c725 if (DPLL0->EN == DPLL_EN_EN) { in dpllState()
731 && (DPLL0->EN != DPLL_EN_EN)) { in dpllState()
743 DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; in dpllState()
744 DPLL0->EN_SET = DPLL_EN_EN; in dpllState()
745 while ((DPLL0->IF & DPLL_IF_LOCK) == 0U) { in dpllState()
754 DPLL0->EN_SET = DPLL_EN_EN; in dpllState()
Dem_cmu.c2508 if (DPLL0->EN == DPLL_EN_EN) { in CMU_HFRCODPLLBandSet()
2509 DPLL0->EN_CLR = DPLL_EN_EN; in CMU_HFRCODPLLBandSet()
2511 while (DPLL0->EN & DPLL_EN_DISABLING) { in CMU_HFRCODPLLBandSet()
2514 while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { in CMU_HFRCODPLLBandSet()
2645 restoreDpll = DPLL0->EN & _DPLL_EN_EN_MASK; in CMU_DPLLLock()
2648 DPLL0->EN_CLR = DPLL_EN_EN; in CMU_DPLLLock()
2650 while (DPLL0->EN & DPLL_EN_DISABLING) { in CMU_DPLLLock()
2653 while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { in CMU_DPLLLock()
2740 DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) in CMU_DPLLLock()
2755 DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) in CMU_DPLLLock()
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/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_emu.c731 if (DPLL0->EN == DPLL_EN_EN) { in dpllState()
737 && (DPLL0->EN != DPLL_EN_EN)) { in dpllState()
749 DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; in dpllState()
750 DPLL0->EN_SET = DPLL_EN_EN; in dpllState()
751 while ((DPLL0->IF & DPLL_IF_LOCK) == 0U) { in dpllState()
760 DPLL0->EN_SET = DPLL_EN_EN; in dpllState()
Dem_cmu.c2537 if (DPLL0->EN == DPLL_EN_EN) { in CMU_HFRCODPLLBandSet()
2538 DPLL0->EN_CLR = DPLL_EN_EN; in CMU_HFRCODPLLBandSet()
2540 while (DPLL0->EN & DPLL_EN_DISABLING) { in CMU_HFRCODPLLBandSet()
2543 while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { in CMU_HFRCODPLLBandSet()
2674 restoreDpll = DPLL0->EN & _DPLL_EN_EN_MASK; in CMU_DPLLLock()
2677 DPLL0->EN_CLR = DPLL_EN_EN; in CMU_DPLLLock()
2679 while (DPLL0->EN & DPLL_EN_DISABLING) { in CMU_DPLLLock()
2682 while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { in CMU_DPLLLock()
2769 DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) in CMU_DPLLLock()
2784 DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) in CMU_DPLLLock()
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/hal_silabs-latest/gecko/emlib/inc/
Dem_cmu.h1478 DPLL0->EN_CLR = DPLL_EN_EN; in CMU_DPLLUnlock()
1480 while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { in CMU_DPLLUnlock()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_cmu.h1479 DPLL0->EN_CLR = DPLL_EN_EN; in CMU_DPLLUnlock()
1481 while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { in CMU_DPLLUnlock()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h863 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21a010f512im32.h863 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21a010f768im32.h863 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21a020f1024im32.h865 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21a020f512im32.h865 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21a020f768im32.h865 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21b010f1024im32.h863 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21b010f512im32.h863 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21b010f768im32.h863 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21b020f1024im32.h865 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21b020f512im32.h865 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Defr32mg21b020f768im32.h865 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
Drm21z000f1024im32.h861 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base po… macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512gn32.h892 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL… macro
Defr32bg22c224f512im32.h892 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL… macro
Defr32bg22e224f512im40.h906 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL… macro
Defr32bg22c112f352gm32.h890 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL… macro
Defr32bg22c224f512im40.h906 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL… macro

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