Searched refs:CONTROL1_SET (Results 1 – 9 of 9) sorted by relevance
364 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK; in _SI32_PBCFG_A_enable_jtag()390 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_ETMEN_MASK; in _SI32_PBCFG_A_enable_etm()416 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_MASK; in _SI32_PBCFG_A_enable_emif_be0_pin()442 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFCS1EN_MASK; in _SI32_PBCFG_A_enable_emif_cs1_pin()468 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFEN_MASK; in _SI32_PBCFG_A_enable_emif()500 basePointer->CONTROL1_SET = in _SI32_PBCFG_A_set_emif_width()529 basePointer->CONTROL1_SET = in _SI32_PBCFG_A_select_port_match_mode_pin_match()544 basePointer->CONTROL1_SET = in _SI32_PBCFG_A_select_port_match_mode_capsense_tx()559 basePointer->CONTROL1_SET = in _SI32_PBCFG_A_select_port_match_mode_capsense_rx()586 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EVREGRMD_MASK; in _SI32_PBCFG_A_select_external_regulator_reset_from_power_on()[all …]
448 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK)474 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_ETMEN_MASK)500 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_MASK)526 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFCS1EN_MASK)552 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFEN_MASK)590 basePointer->CONTROL1_SET =\625 basePointer->CONTROL1_SET =\641 basePointer->CONTROL1_SET =\657 basePointer->CONTROL1_SET =\685 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EVREGRMD_MASK)[all …]
1316 volatile uint32_t CONTROL1_SET; member
446 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK)472 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_ETMEN_MASK)498 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_MASK)524 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFCS1EN_MASK)550 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EMIFEN_MASK)588 basePointer->CONTROL1_SET =\623 basePointer->CONTROL1_SET =\639 basePointer->CONTROL1_SET =\655 basePointer->CONTROL1_SET =\683 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_EVREGRMD_MASK)[all …]
416 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK; in _SI32_PBCFG_A_enable_jtag()442 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_ETMEN_MASK; in _SI32_PBCFG_A_enable_etm()469 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_SWVEN_MASK; in _SI32_PBCFG_A_enable_swv()498 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_SPI1SEL_MASK; in _SI32_PBCFG_A_enable_spi1_on_crossbar()526 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_PMATCHEN_MASK; in _SI32_PBCFG_A_enable_port_match_interrupt()565 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_LPTOSEL_MASK; in _SI32_PBCFG_A_enable_low_power_timer_output1()593 basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_LOCK_MASK; in _SI32_PBCFG_A_lock_port_registers()
495 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK)521 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_ETMEN_MASK)550 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_SWVEN_MASK)583 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_SPI1SEL_MASK)613 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_PMATCHEN_MASK)652 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_LPTOSEL_MASK)684 (basePointer->CONTROL1_SET = SI32_PBCFG_A_CONTROL1_LOCK_MASK)
765 volatile uint32_t CONTROL1_SET; member
