Searched refs:CONTROL1_CLR (Results 1 – 9 of 9) sorted by relevance
377 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK; in _SI32_PBCFG_A_disable_jtag()403 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_ETMEN_MASK; in _SI32_PBCFG_A_disable_etm()429 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_MASK; in _SI32_PBCFG_A_disable_emif_be0_pin()455 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFCS1EN_MASK; in _SI32_PBCFG_A_disable_emif_cs1_pin()481 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFEN_MASK; in _SI32_PBCFG_A_disable_emif()499 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFWIDTH_MASK; in _SI32_PBCFG_A_set_emif_width()528 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK; in _SI32_PBCFG_A_select_port_match_mode_pin_match()543 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK; in _SI32_PBCFG_A_select_port_match_mode_capsense_tx()558 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK; in _SI32_PBCFG_A_select_port_match_mode_capsense_rx()573 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EVREGRMD_MASK; in _SI32_PBCFG_A_select_external_regulator_reset_from_all_sources()[all …]
461 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK)487 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_ETMEN_MASK)513 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_MASK)539 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFCS1EN_MASK)565 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFEN_MASK)589 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFWIDTH_MASK;\624 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK;\640 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK;\656 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK;\672 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EVREGRMD_MASK)[all …]
1317 volatile uint32_t CONTROL1_CLR; member
459 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK)485 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_ETMEN_MASK)511 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFBE0BEN_MASK)537 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFCS1EN_MASK)563 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFEN_MASK)587 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EMIFWIDTH_MASK;\622 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK;\638 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK;\654 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_MATMD_MASK;\670 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_EVREGRMD_MASK)[all …]
429 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK; in _SI32_PBCFG_A_disable_jtag()455 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_ETMEN_MASK; in _SI32_PBCFG_A_disable_etm()483 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_SWVEN_MASK; in _SI32_PBCFG_A_disable_swv()513 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_SPI1SEL_MASK; in _SI32_PBCFG_A_disable_spi1_on_crossbar()539 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_PMATCHEN_MASK; in _SI32_PBCFG_A_disable_port_match_interrupt()552 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_LPTOSEL_MASK; in _SI32_PBCFG_A_enable_low_power_timer_output0()579 basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_LOCK_MASK; in _SI32_PBCFG_A_unlock_port_registers()
508 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_JTAGEN_MASK)534 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_ETMEN_MASK)566 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_SWVEN_MASK)600 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_SPI1SEL_MASK)626 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_PMATCHEN_MASK)639 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_LPTOSEL_MASK)668 (basePointer->CONTROL1_CLR = SI32_PBCFG_A_CONTROL1_LOCK_MASK)
766 volatile uint32_t CONTROL1_CLR; member
