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Searched refs:_WDOG_CFG_PRS1MISSRSTEN_DEFAULT (Results 1 – 4 of 4) sorted by relevance

/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21_wdog.h181 #define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode D… macro
182 #define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifte…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_wdog.h181 #define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode D… macro
182 #define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifte…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_wdog.h181 #define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode D… macro
182 #define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifte…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24_wdog.h195 #define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode D… macro
196 #define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifte…