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Searched refs:_SMU_PPUPATD1_PDM_DEFAULT (Results 1 – 25 of 37) sorted by relevance

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/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h287 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
288 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b390f1024gl112.h7732 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
7733 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b390f512gl112.h7732 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
7733 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b110f1024gq64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b110f1024gm64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b110f1024iq64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b530f512iq64.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b530f512il112.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b530f512il120.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b530f512im64.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b110f1024im64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b530f512iq100.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b530f512gq100.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b530f512gq64.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b310f1024gl112.h8538 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8539 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b510f1024gl112.h8540 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8541 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b310f1024gq100.h8538 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8539 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b330f512gl112.h8538 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8539 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b130f512gq64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b330f512gq100.h8538 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8539 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b130f512im64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b130f512gm64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
Defm32gg12b130f512iq64.h8504 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8505 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode …
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_smu.h466 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000001UL /**< Mode… macro
467 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 2) /**< Shif…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_smu.h466 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000001UL /**< Mode… macro
467 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 2) /**< Shif…

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