_MSC_STATUS_REGLOCK_DEFAULT (reference) in projects: hal_silabs-3.6.0

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Searched refs:_MSC_STATUS_REGLOCK_DEFAULT (Results 1 – 4 of 4) sorted by relevance

/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
D	efr32mg21_msc.h	`305 #define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /… macro 308 #define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /…`
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
D	efr32bg27_msc.h	`328 #define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /… macro 331 #define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /…`
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
D	efr32bg22_msc.h	`309 #define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /… macro 312 #define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /…`
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
D	efr32mg24_msc.h	`344 #define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /… macro 347 #define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /…`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
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