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Searched refs:DMEM_S_BASE (Results 1 – 25 of 41) sorted by relevance

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/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24a020f1024im48.h552 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
791 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
921 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a020f1536gm40.h550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a020f1536gm48.h552 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
791 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
921 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a020f1536im40.h550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a020f1536im48.h552 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
791 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
921 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a020f768im40.h550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a021f1024im40.h547 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
786 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
916 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a110f1024im48.h550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a110f1536gm48.h550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a111f1536gm48.h549 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
788 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
918 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a120f1536gm48.h548 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
787 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
917 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a121f1536gm48.h547 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
786 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
916 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a410f1536im40.h552 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
791 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
921 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a410f1536im48.h554 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
793 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
923 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a420f1536im40.h550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a420f1536im48.h552 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
791 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
921 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a610f1536im40.h552 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
791 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
921 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24a620f1536im40.h550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24b010f1024im48.h555 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
794 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
924 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24b010f1536im40.h553 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
792 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
922 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24b010f1536im48.h555 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
794 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
924 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24b020f1024im48.h553 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
792 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
922 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24b020f1536im40.h551 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
790 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
920 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24b020f1536im48.h553 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
792 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
922 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…
Defr32mg24b110f1536gm48.h551 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ macro
790 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */
920 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base p…

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