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Searched refs:_PRS_CH_CTRL_SOURCESEL_TIMER0 (Results 1 – 25 of 125) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg_prs.h274 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIM… macro
288 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted …
Defm32hg110f32.h1739 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIM… macro
1752 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted …
Defm32hg110f64.h1739 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIM… macro
1752 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted …
Defm32hg210f32.h1739 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIM… macro
1752 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted …
Defm32hg210f64.h1739 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIM… macro
1752 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted …
Defm32hg222f32.h1739 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIM… macro
1752 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted …
Defm32hg222f64.h1739 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIM… macro
1752 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted …
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32WG/Include/
Defm32wg_prs.h400 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
424 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg880f128.h2038 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2061 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg890f256.h2038 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2061 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg895f128.h2038 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2061 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg895f256.h2038 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2061 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg895f64.h2038 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2061 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg295f256.h1985 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2008 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg280f128.h1985 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2008 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
Defm32wg280f256.h1985 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mo… macro
2008 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Sh…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_prs.h894 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode… macro
912 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shif…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_prs.h894 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode… macro
912 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shif…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_prs.h992 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /… macro
1018 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_prs.h992 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /… macro
1018 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_prs.h1094 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /… macro
1134 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_prs.h1022 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /… macro
1051 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_prs.h1022 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /… macro
1051 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_prs.h1022 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /… macro
1051 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_prs.h1470 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /… macro
1517 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /…

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