_CMU_LFEPRESC0_RTCC_DIV2 (reference) in projects: hal_silabs-3.5.0

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Searched refs:_CMU_LFEPRESC0_RTCC_DIV2 (Results 1 – 25 of 79) sorted by relevance

12 3 4

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
D	efm32pg12b_cmu.h	`1778 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 1781 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
D	efm32jg12b_cmu.h	`1778 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 1781 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
D	efr32mg12p_cmu.h	`1778 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 1781 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
D	efr32bg13p_cmu.h	`1850 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 1853 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p632f512gm32.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p532f512gm48.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p632f512gm48.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p532f512gm32.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p733f512gm48.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p732f512gm32.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p632f512im48.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p732f512gm48.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efr32bg13p632f512im32.h	`4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
D	efr32fg13p_cmu.h	`1850 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 1853 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
D	efm32gg12b_cmu.h	`2222 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 2225 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b390f1024gl112.h	`6038 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6041 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b390f512gl112.h	`6038 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6041 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b110f1024iq64.h	`6836 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6839 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b510f1024gl120.h	`6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b510f1024gm64.h	`6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b510f1024gl112.h	`6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b530f512im64.h	`6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
D	efm32gg12b530f512iq64.h	`6867 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 6870 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
D	efm32gg11b_cmu.h	`2289 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /< Mode… macro 2292 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /< Shif…`
/hal_silabs-3.5.0/gecko/emlib/src/
D	em_cmu.c	`7899 #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) in CMU_ClockPrescSet() 7900 EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); in CMU_ClockPrescSet() 8052 #elif defined(_CMU_LFEPRESC0_RTCC_DIV2) in CMU_ClockPrescSet() 8053 EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); in CMU_ClockPrescSet()`

12 3 4

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
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Zephyr-Core-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
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babblesim_ext_2G4_phy_v1-3.7.0
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