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Searched refs:_CMU_ADCCTRL_ADC0CLKSEL_HFXO (Results 1 – 25 of 82) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_cmu.h1694 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
1699 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_cmu.h1694 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
1699 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_cmu.h1915 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
1920 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_cmu.h1915 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
1920 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_cmu.h1915 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
1920 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_cmu.h1969 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
1974 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p632f512gm32.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p532f512gm48.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p632f512gm48.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p532f512gm32.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p733f512gm48.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p732f512gm32.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p632f512im48.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p732f512gm48.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
Defr32bg13p632f512im32.h4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_cmu.h1969 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /… macro
1974 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_cmu.h2375 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
2380 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
Defm32gg12b390f1024gl112.h6191 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
6196 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
Defm32gg12b390f512gl112.h6191 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
6196 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
Defm32gg12b110f1024iq64.h6989 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
6994 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
Defm32gg12b510f1024gl120.h7020 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
7025 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
Defm32gg12b510f1024gm64.h7020 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
7025 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
Defm32gg12b510f1024gl112.h7020 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
7025 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_cmu.h2442 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL … macro
2447 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) …
/hal_silabs-3.5.0/gecko/emlib/inc/
Dsli_em_cmu.h1636 | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \

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