Home
last modified time | relevance | path

Searched refs:TIMER0_S_BASE (Results 1 – 21 of 21) sorted by relevance

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h474 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
631 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
794 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21a010f512im32.h474 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
631 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
794 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21a010f768im32.h474 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
631 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
794 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21a020f1024im32.h476 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
633 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
796 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21a020f512im32.h476 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
633 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
796 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21a020f768im32.h476 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
633 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
796 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21b010f1024im32.h474 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
631 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
794 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21b010f768im32.h474 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
631 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
794 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21b020f1024im32.h476 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
633 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
796 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21b010f512im32.h474 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
631 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
794 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21b020f512im32.h476 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
633 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
796 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg21b020f768im32.h476 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
633 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
796 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Drm21z000f1024im32.h472 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
629 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
792 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512im40.h508 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
667 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
835 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIME…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27c230f768im32.h542 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
701 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
869 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base po…
Defr32bg27c230f768im40.h562 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
721 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
889 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base po…
Defr32bg27c140f768im32.h547 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
706 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
874 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base po…
Defr32bg27c140f768im40.h563 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
722 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
890 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base po…
Defr32bg27c320f768gj39.h548 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
707 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
875 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base po…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24b310f1536im48.h541 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
716 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
924 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…
Defr32mg24b220f1536im48.h540 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ macro
713 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */
916 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base…