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Searched refs:HFRCO0 (Results 1 – 25 of 27) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG27/Source/
Dsystem_efr32bg27.c216 switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) in SystemHFRCODPLLClockGet()
219 switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { in SystemHFRCODPLLClockGet()
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Source/
Dsystem_efr32bg22.c214 switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) in SystemHFRCODPLLClockGet()
217 switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { in SystemHFRCODPLLClockGet()
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Source/
Dsystem_efr32mg21.c214 switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) in SystemHFRCODPLLClockGet()
217 switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { in SystemHFRCODPLLClockGet()
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Source/
Dsystem_efr32mg24.c216 switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) in SystemHFRCODPLLClockGet()
219 switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { in SystemHFRCODPLLClockGet()
/hal_silabs-3.5.0/gecko/emlib/src/
Dem_cmu.c2433 while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { in CMU_HFRCODPLLBandSet()
2443 hfrcoCalCurrent = HFRCO0->CAL; in CMU_HFRCODPLLBandSet()
2444 HFRCO0->CAL = freqCal; in CMU_HFRCODPLLBandSet()
2448 hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); in CMU_HFRCODPLLBandSet()
2456 HFRCO0->CAL = hfrcoCalCurrent; in CMU_HFRCODPLLBandSet()
2598 while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { in CMU_DPLLLock()
2608 hfrcoCalCurrent = HFRCO0->CAL; in CMU_DPLLLock()
2609 HFRCO0->CAL = hfrcoCalVal; in CMU_DPLLLock()
2613 hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); in CMU_DPLLLock()
2641 HFRCO0->CAL = hfrcoCalCurrent; in CMU_DPLLLock()
[all …]
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h868 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1188 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1191 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21a010f512im32.h868 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1188 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1191 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21a010f768im32.h868 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1188 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1191 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21a020f1024im32.h870 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1190 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1193 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21a020f512im32.h870 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1190 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1193 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21a020f768im32.h870 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1190 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1193 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21b010f1024im32.h868 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1188 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1191 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21b010f768im32.h868 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1188 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1191 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21b020f1024im32.h870 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1190 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1193 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21b010f512im32.h868 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1188 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1191 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21b020f512im32.h870 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1190 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1193 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg21b020f768im32.h870 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1190 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1193 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Drm21z000f1024im32.h866 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1186 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1189 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24b310f1536im48.h1016 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1418 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1421 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
Defr32mg24b220f1536im48.h1006 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base p… macro
1406 #define HFRCO(n) (((n) == 0) ? HFRCO0 \
1409 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Source/IAR/
Dstartup_efr32mg21.s137 DCD HFRCO0_IRQHandler ; 46: HFRCO0 Interrupt
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512im40.h911 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRC… macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27c230f768im32.h945 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base poin… macro
Defr32bg27c230f768im40.h965 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base poin… macro
Defr32bg27c140f768im32.h950 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base poin… macro

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