DPLL0_S_BASE (reference) in projects: hal_silabs-3.5.0

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Searched refs:DPLL0_S_BASE (Results 1 – 21 of 21) sorted by relevance

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
D	efr32mg21a010f1024im32.h	`464 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 581 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 784 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21a010f512im32.h	`464 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 581 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 784 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21a010f768im32.h	`464 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 581 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 784 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21a020f1024im32.h	`466 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 583 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 786 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21a020f512im32.h	`466 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 583 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 786 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21a020f768im32.h	`466 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 583 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 786 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21b010f1024im32.h	`464 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 581 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 784 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21b010f768im32.h	`464 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 581 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 784 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21b020f1024im32.h	`466 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 583 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 786 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21b010f512im32.h	`464 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 581 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 784 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21b020f512im32.h	`466 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 583 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 786 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg21b020f768im32.h	`466 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 583 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 786 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	rm21z000f1024im32.h	`462 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 579 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 782 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
D	efr32bg22c224f512im40.h	`498 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 617 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 825 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
D	efr32bg27c230f768im32.h	`532 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 651 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 859 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base poi…`
D	efr32bg27c230f768im40.h	`552 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 671 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 879 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base poi…`
D	efr32bg27c140f768im32.h	`537 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 656 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 864 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base poi…`
D	efr32bg27c140f768im40.h	`553 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 672 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 880 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base poi…`
D	efr32bg27c320f768gj39.h	`538 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 657 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 865 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base poi…`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
D	efr32mg24b310f1536im48.h	`531 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 666 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 914 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`
D	efr32mg24b220f1536im48.h	`530 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address / macro 663 #define DPLL0_BASE (DPLL0_S_BASE) / DPLL0 base address / 906 #define DPLL0_S ((DPLL_TypeDef ) DPLL0_S_BASE) /**< DPLL0_S base …`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
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babblesim_base-3.6.0-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
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babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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edtt-3.7.0
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