Home
last modified time | relevance | path

Searched refs:CMU_HFXOCTRL1_PEAKDETTHR_THR2 (Results 1 – 25 of 64) sorted by relevance

123

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_cmu.h526 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b390f1024gl112.h4362 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b390f512gl112.h4362 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b110f1024iq64.h5193 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024gl120.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024gm64.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024gl112.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b530f512im64.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b530f512iq64.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b130f512gm64.h5193 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b130f512gq64.h5193 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b130f512im64.h5193 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b130f512iq64.h5193 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b530f512iq100.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b110f1024gm64.h5193 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b110f1024gq64.h5193 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024iq100.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024gq64.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024il112.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024im64.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024il120.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b510f1024gq100.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b530f512gm64.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
Defm32gg12b530f512gl120.h5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_cmu.h526 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) … macro

123