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Searched refs:AMUXCP0_S_BASE (Results 1 – 15 of 15) sorted by relevance

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h499 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
819 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21a010f512im32.h499 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
819 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21a010f768im32.h499 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
819 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21a020f1024im32.h501 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
821 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21a020f512im32.h501 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
821 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21a020f768im32.h501 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
821 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21b010f1024im32.h499 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
819 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21b010f768im32.h499 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
819 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21b020f1024im32.h501 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
821 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21b010f512im32.h499 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
819 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21b020f512im32.h501 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
821 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Defr32mg21b020f768im32.h501 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
821 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
Drm21z000f1024im32.h497 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
754 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
817 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512im40.h531 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ macro
782 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
858 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUX…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24b310f1536im48.h566 #define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ macro
841 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */
949 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S bas…