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Searched refs:AMUXCP0_BASE (Results 1 – 15 of 15) sorted by relevance

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
905 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21a010f512im32.h756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
905 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21a010f768im32.h756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
905 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21a020f1024im32.h758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
760 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
907 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21a020f512im32.h758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
760 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
907 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21a020f768im32.h758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
760 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
907 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21b010f1024im32.h756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
905 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21b010f768im32.h756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
905 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21b020f1024im32.h758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
760 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
907 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21b010f512im32.h756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
758 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
905 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21b020f512im32.h758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
760 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
907 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Defr32mg21b020f768im32.h758 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
760 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
907 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
Drm21z000f1024im32.h754 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
756 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
903 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512im40.h782 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
784 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
946 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUX…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24b310f1536im48.h841 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ macro
843 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ macro
1053 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base …