Home
last modified time | relevance | path

Searched refs:ADCCTRL (Results 1 – 25 of 82) sorted by relevance

1234

/hal_silabs-3.5.0/gecko/emlib/inc/
Dsli_em_cmu.h1621 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \
1628 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \
1635 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \
1641 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \
1649 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \
1656 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \
1663 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \
1669 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \
/hal_silabs-3.5.0/gecko/emlib/src/
Dem_cmu.c7509 ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockFreqGet()
7519 ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) in CMU_ClockFreqGet()
7740 ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescGet()
7746 ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) in CMU_ClockPrescGet()
8079 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescSet()
8087 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK) in CMU_ClockPrescSet()
8478 switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) { in CMU_ClockSelectGet()
8504 switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) { in CMU_ClockSelectGet()
9540 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) in CMU_ClockSelectSet()
9575 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) in CMU_ClockSelectSet()
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_cmu.h125 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_cmu.h125 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_cmu.h128 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_cmu.h128 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_cmu.h128 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_cmu.h128 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p632f512gm32.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p532f512gm48.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p632f512gm48.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p532f512gm32.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p733f512gm48.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p732f512gm32.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p632f512im48.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p732f512gm48.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defr32bg13p632f512im32.h433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_cmu.h128 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_cmu.h127 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defm32gg12b390f1024gl112.h550 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defm32gg12b390f512gl112.h550 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defm32gg12b110f1024iq64.h591 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defm32gg12b510f1024gl120.h596 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
Defm32gg12b510f1024gm64.h596 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_cmu.h127 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ member

1234