Searched refs:nvic_hw (Results 1 – 4 of 4) sorted by relevance
385 nvic_hw->icpr[int_num/32] = 1 << (int_num % 32); in irq_clear()487 if (ns) nvic_hw->itns[irq_num >> 5] |= 1u << (irq_num & 0x1fu); in irq_assign_to_ns()488 else nvic_hw->itns[irq_num >> 5] &= ~(1u << (irq_num & 0x1fu)); in irq_assign_to_ns()
74 return 0 != (nvic_hw->iser[num/32] & (1 << num % 32)); in pico_irq_is_enabled()93 nvic_hw->icpr = mask; in irq_set_mask_n_enabled_internal()94 nvic_hw->iser = mask; in irq_set_mask_n_enabled_internal()96 nvic_hw->icer = mask; in irq_set_mask_n_enabled_internal()101 nvic_hw->icpr[n] = mask; in irq_set_mask_n_enabled_internal()102 nvic_hw->iser[n] = mask; in irq_set_mask_n_enabled_internal()104 nvic_hw->icer[n] = mask; in irq_set_mask_n_enabled_internal()127 nvic_hw->ispr[num/32] = 1 << (num % 32); in irq_set_pending()
65 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) macro
89 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET)) macro
