Searched refs:dma_hw (Results 1 – 5 of 5) sorted by relevance
73 return &dma_hw->ch[channel]; in dma_channel_hw_addr()492 dma_hw->multi_channel_trigger = chan_mask; in dma_start_channel_mask()546 dma_hw->abort = 1u << channel; in dma_channel_abort()549 while (dma_hw->ch[channel].ctrl_trig & DMA_CH0_CTRL_TRIG_BUSY_BITS) tight_loop_contents(); in dma_channel_abort()562 hw_set_bits(&dma_hw->inte0, 1u << channel); in dma_channel_set_irq0_enabled()564 hw_clear_bits(&dma_hw->inte0, 1u << channel); in dma_channel_set_irq0_enabled()575 hw_set_bits(&dma_hw->inte0, channel_mask); in dma_set_irq0_channel_mask_enabled()577 hw_clear_bits(&dma_hw->inte0, channel_mask); in dma_set_irq0_channel_mask_enabled()591 hw_set_bits(&dma_hw->inte1, 1u << channel); in dma_channel_set_irq1_enabled()593 hw_clear_bits(&dma_hw->inte1, 1u << channel); in dma_channel_set_irq1_enabled()[all …]
88 dma_hw->ints0 |= 1u; in test_irq_handler0()110 dma_hw->ints1 |= 2u; in test_irq_handler1()152 dma_hw->timer[0] = (1 << 16) | 32; // run at 1/32 system clock in test_nesting()
76 …hw_write_masked( &dma_hw->ch[channel].al1_ctrl, (channel << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB) | (0u … in dma_channel_cleanup()83 dma_hw->intr = 1u << channel; in dma_channel_cleanup()
235 #define dma_hw ((dma_hw_t *)DMA_BASE) macro
332 #define dma_hw ((dma_hw_t *)DMA_BASE) macro
