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Searched refs:csr (Results 1 – 10 of 10) sorted by relevance

/hal_rpi_pico-latest/src/rp2_common/hardware_hazard3/include/hardware/
Dhazard3.h33 #define hazard3_irqarray_read(csr, index) (riscv_read_set_csr(csr, (index)) >> 16) argument
35 #define hazard3_irqarray_read(csr, index) static_assert(false, "Not supported: Xh3irq extension")
39 #define hazard3_irqarray_write(csr, index, data) (riscv_write_csr(csr, (index) | ((uint32_t)(data) … argument
41 #define hazard3_irqarray_write(csr, index, data) static_assert(false, "Not supported: Xh3irq extens…
45 #define hazard3_irqarray_set(csr, index, data) (riscv_set_csr(csr, (index) | ((uint32_t)(data) << 1… argument
47 #define hazard3_irqarray_set(csr, index, data) static_assert(false, "Not supported: Xh3irq extensio…
51 #define hazard3_irqarray_clear(csr, index, data) (riscv_clear_csr(csr, (index) | ((uint32_t)(data) … argument
53 #define hazard3_irqarray_clear(csr, index, data) static_assert(false, "Not supported: Xh3irq extens…
/hal_rpi_pico-latest/src/rp2_common/hardware_sha256/include/hardware/
Dsha256.h79 hw_write_masked(&sha256_hw->csr, val << SHA256_CSR_DMA_SIZE_LSB, SHA256_CSR_DMA_SIZE_BITS); in sha256_set_dma_size()
93 hw_set_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); in sha256_set_bswap()
95 hw_clear_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); in sha256_set_bswap()
105 hw_set_bits(&sha256_hw->csr, SHA256_CSR_START_BITS); in sha256_start()
118 return sha256_hw->csr & SHA256_CSR_SUM_VLD_BITS; in sha256_is_sum_valid()
130 return sha256_hw->csr & SHA256_CSR_WDATA_RDY_BITS; in sha256_is_ready()
175 return sha256_hw->csr & SHA256_CSR_ERR_WDATA_NOT_RDY_BITS; in sha256_err_not_ready()
184 hw_clear_bits(&sha256_hw->csr, SHA256_CSR_ERR_WDATA_NOT_RDY_BITS); in sha256_err_not_ready_clear()
/hal_rpi_pico-latest/test/hardware_pwm_test/
Dhardware_pwm_test.c65 PICOTEST_CHECK_CHANNEL(pwm, slice->csr == in main()
106 … !(slice->csr & PWM_CH0_CSR_A_INV_BITS) && !(slice->csr & PWM_CH0_CSR_B_INV_BITS), in main()
110 …PICOTEST_CHECK_CHANNEL(pwm, (slice->csr & PWM_CH0_CSR_A_INV_BITS) && !(slice->csr & PWM_CH0_CSR_B_… in main()
114 …PICOTEST_CHECK_CHANNEL(pwm, !(slice->csr & PWM_CH0_CSR_A_INV_BITS) && (slice->csr & PWM_CH0_CSR_B_… in main()
118 …PICOTEST_CHECK_CHANNEL(pwm, (slice->csr & PWM_CH0_CSR_A_INV_BITS) && (slice->csr & PWM_CH0_CSR_B_I… in main()
122 …PICOTEST_CHECK_CHANNEL(pwm, (slice->csr & PWM_CH0_CSR_PH_CORRECT_BITS), "pwm_set_phase_correct(T)"… in main()
125 …PICOTEST_CHECK_CHANNEL(pwm, !(slice->csr & PWM_CH0_CSR_PH_CORRECT_BITS), "pwm_set_phase_correct(F)… in main()
129 …PICOTEST_CHECK_CHANNEL(pwm, ((slice->csr & PWM_CH0_CSR_DIVMODE_BITS) >> PWM_CH0_CSR_DIVMODE_LSB) =… in main()
/hal_rpi_pico-latest/src/rp2_common/hardware_pwm/include/hardware/
Dpwm.h69 uint32_t csr; member
147 c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS) in pwm_config_set_phase_correct()
223 c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS) in pwm_config_set_clkdiv_mode()
235 c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS)) in pwm_config_set_output_polarity()
264 pwm_hw->slice[slice_num].csr = 0; in pwm_init()
270 pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB); in pwm_init()
416 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS); in pwm_advance_count()
417 while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) { in pwm_advance_count()
433 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS); in pwm_retard_count()
434 while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) { in pwm_retard_count()
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/hal_rpi_pico-latest/src/rp2350/hardware_structs/include/hardware/structs/
Dsha256.h35 io_rw_32 csr;
Dhstx_ctrl.h36 io_rw_32 csr;
Dsystick.h37 io_rw_32 csr;
Dpwm.h36 io_rw_32 csr;
/hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/
Dsystick.h33 io_rw_32 csr;
Dpwm.h36 io_rw_32 csr;