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Searched refs:R_SYSC_NS (Results 1 – 6 of 6) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c338 R_SYSC_NS->SCKCR = sckcr; in bsp_prv_clock_set()
343 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
344 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
345 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
346 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
347 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
348 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
349 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
350 dummy = R_SYSC_NS->SCKCR; in bsp_prv_clock_set()
353 R_SYSC_NS->SCKCR3 = sckcr3; in bsp_prv_clock_set()
[all …]
Dbsp_module_stop.h57 #define BSP_MSTP_REG_FSP_IP_BSC(channel) R_SYSC_NS->MSTPCRA
61 #define BSP_MSTP_REG_FSP_IP_XSPI(channel) R_SYSC_NS->MSTPCRA
65 #define BSP_MSTP_REG_FSP_IP_SCI(channel) *((4U >= channel) ? &R_SYSC_NS->MSTPCRA : &R_SY…
84 #define BSP_MSTP_REG_FSP_IP_SCIE(channel) R_SYSC_NS->MSTPCRA
100 #define BSP_MSTP_REG_FSP_IP_IIC(channel) *((1U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SY…
105 #define BSP_MSTP_REG_FSP_IP_SPI(channel) *((2U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SY…
113 #define BSP_MSTP_REG_FSP_IP_MTU3(channel) R_SYSC_NS->MSTPCRC
118 …#define BSP_MSTP_REG_FSP_IP_GPT(channel) *((13U >= channel) ? &R_SYSC_NS->MSTPCRC : &R_S…
126 …#define BSP_MSTP_REG_FSP_IP_GPT(channel) *((51U >= channel) ? &R_SYSC_NS->MSTPCRC : &R_S…
153 #define BSP_MSTP_REG_FSP_IP_TFU(channel) R_SYSC_NS->MSTPCRC
[all …]
Dbsp_reset.c320 p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + in R_BSP_ModuleResetEnable()
352 p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + in R_BSP_ModuleResetDisable()
/hal_renesas-latest/zephyr/rz/portable/rzn/
Dbsp_common.h478 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI0ASYNCSEL]; in R_FSP_SystemClockHzGet()
480 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI0ASYNCSEL]; in R_FSP_SystemClockHzGet()
488 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI1ASYNCSEL]; in R_FSP_SystemClockHzGet()
490 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI1ASYNCSEL]; in R_FSP_SystemClockHzGet()
498 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI2ASYNCSEL]; in R_FSP_SystemClockHzGet()
500 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI2ASYNCSEL]; in R_FSP_SystemClockHzGet()
514 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI0ASYNCSEL]; in R_FSP_SystemClockHzGet()
516 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI0ASYNCSEL]; in R_FSP_SystemClockHzGet()
524 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI1ASYNCSEL]; in R_FSP_SystemClockHzGet()
526 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI1ASYNCSEL]; in R_FSP_SystemClockHzGet()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Source/
Dsystem.c1253 …if ((0 == R_SYSC_NS->RSTSR0_b.SWR0F) && (0 == R_SYSC_NS->RSTSR0_b.SWR550) && (0 == R_SYSC_NS->RSTS… in bsp_copy_to_ram()
1255 if (0 == R_SYSC_NS->RSTSR0_b.SWR0F) in bsp_copy_to_ram()
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h30848 #define R_SYSC_NS ((R_SYSC_NS_Type *) R_SYSC_NS_BASE) macro