Home
last modified time | relevance | path

Searched refs:R_CLMA3 (Results 1 – 3 of 3) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c652 R_CLMA3->CMPL = BSP_CFG_CLMA3_CMPL; in bsp_clock_init()
653 R_CLMA3->CMPH = BSP_CFG_CLMA3_CMPH; in bsp_clock_init()
658 R_CLMA3->PCMD = BSP_PRV_PCMD_KEY; in bsp_clock_init()
660 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
661 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; in bsp_clock_init()
662 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
664 if (1 != R_CLMA3->CTL0) in bsp_clock_init()
667 dummy = R_CLMA3->PROTSR; in bsp_clock_init()
669 } while (1 == R_CLMA3->PROTSR_b.PRERR); in bsp_clock_init()
Dbsp_module_stop.h283R_CLMA3-> \
292 ((3 >= channel) ? R_CLMA3->CTL0 : \
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h30872 #define R_CLMA3 ((R_CLMA0_Type *) R_CLMA3_BASE) macro