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Searched refs:R_CLMA2 (Results 1 – 3 of 3) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c629 R_CLMA2->CMPL = BSP_CFG_CLMA2_CMPL; in bsp_clock_init()
630 R_CLMA2->CMPH = BSP_CFG_CLMA2_CMPH; in bsp_clock_init()
635 R_CLMA2->PCMD = BSP_PRV_PCMD_KEY; in bsp_clock_init()
637 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
638 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; in bsp_clock_init()
639 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
641 if (1 != R_CLMA2->CTL0) in bsp_clock_init()
644 dummy = R_CLMA2->PROTSR; in bsp_clock_init()
646 } while (1 == R_CLMA2->PROTSR_b.PRERR); in bsp_clock_init()
Dbsp_module_stop.h281R_CLMA2-> \
291 ((2 >= channel) ? R_CLMA2->CTL0 : \
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h30871 #define R_CLMA2 ((R_CLMA0_Type *) R_CLMA2_BASE) macro