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Searched refs:R_CLMA1 (Results 1 – 3 of 3) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c606 R_CLMA1->CMPL = BSP_CFG_CLMA1_CMPL; in bsp_clock_init()
607 R_CLMA1->CMPH = BSP_CFG_CLMA1_CMPH; in bsp_clock_init()
612 R_CLMA1->PCMD = BSP_PRV_PCMD_KEY; in bsp_clock_init()
614 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
615 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; in bsp_clock_init()
616 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
618 if (1 != R_CLMA1->CTL0) in bsp_clock_init()
621 dummy = R_CLMA1->PROTSR; in bsp_clock_init()
623 } while (1 == R_CLMA1->PROTSR_b.PRERR); in bsp_clock_init()
Dbsp_module_stop.h278 … channel) ? R_CLMA1->CTL0 : ((2 >= \
290 ((1 >= channel) ? R_CLMA1->CTL0 : \
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h30870 #define R_CLMA1 ((R_CLMA0_Type *) R_CLMA1_BASE) macro