Searched refs:CTL0 (Results 1 – 3 of 3) sorted by relevance
591 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()592 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; in bsp_clock_init()593 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()595 if (1 != R_CLMA0->CTL0) in bsp_clock_init()614 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()615 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; in bsp_clock_init()616 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()618 if (1 != R_CLMA1->CTL0) in bsp_clock_init()637 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()638 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; in bsp_clock_init()[all …]
277 … channel) ? R_CLMA0->CTL0 : ((1 >= \278 … channel) ? R_CLMA1->CTL0 : ((2 >= \282 … CTL0 : \284 … CTL0));289 #define BSP_MSTP_DMY_FSP_IP_CLMA(channel) ((0 >= channel) ? R_CLMA0->CTL0 : \290 ((1 >= channel) ? R_CLMA1->CTL0 : \291 ((2 >= channel) ? R_CLMA2->CTL0 : \292 ((3 >= channel) ? R_CLMA3->CTL0 : \293 ((4 >= channel) ? R_CLMA4->CTL0 : \294 ((5 >= channel) ? R_CLMA5->CTL0 : \[all …]
27675 …__IOM uint8_t CTL0; /*!< (@ 0x00000000) CLMA Control Register 0 … member
