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Searched refs:CRG_XTAL (Results 1 – 4 of 4) sorted by relevance

/hal_renesas-latest/smartbond/da1469x_hal/
Dda1469x_clock.c50 CRG_XTAL->CLK_FREQ_TRIM_REG = \
51 ((CRG_XTAL->CLK_FREQ_TRIM_REG & ~CRG_XTAL_CLK_FREQ_TRIM_REG_ ## _field ## _Msk) | \
56 ((CRG_XTAL->CLK_FREQ_TRIM_REG & CRG_XTAL_CLK_FREQ_TRIM_REG_ ## _field ## _Msk) >> \
60 CRG_XTAL->XTAL32M_CTRL2_REG = \
61 ((CRG_XTAL->XTAL32M_CTRL2_REG & ~CRG_XTAL_XTAL32M_CTRL2_REG_ ## _field ## _Msk) | \
66 ((CRG_XTAL->XTAL32M_CTRL2_REG & CRG_XTAL_XTAL32M_CTRL2_REG_ ## _field ## _Msk) >> \
70 CRG_XTAL->XTALRDY_CTRL_REG = \
71 ((CRG_XTAL->XTALRDY_CTRL_REG & ~CRG_XTAL_XTALRDY_CTRL_REG_ ## _field ## _Msk) | \
76 ((CRG_XTAL->XTALRDY_CTRL_REG & CRG_XTAL_XTALRDY_CTRL_REG_ ## _field ## _Msk) >> \
80 ((CRG_XTAL->XTALRDY_STAT_REG & CRG_XTAL_XTALRDY_STAT_REG_ ## _field ## _Msk) >> \
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Dda1469x_pd.c166 write32_mask(0x3ff00000, 0x000afd70, REG_TO_PTR(CRG_XTAL->CLK_FREQ_TRIM_REG)); in da1469x_TSMC_pd_apply_preferred()
167 write32_mask(0x000000c0, 0x00000562, REG_TO_PTR(CRG_XTAL->TRIM_CTRL_REG)); in da1469x_TSMC_pd_apply_preferred()
168 write32_mask(0x03c38002, 0x0801e6b6, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL0_REG)); in da1469x_TSMC_pd_apply_preferred()
169 write32_mask(0x007fff00, 0x7500a1a4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL1_REG)); in da1469x_TSMC_pd_apply_preferred()
170 write32_mask(0x00000fff, 0x001e45c4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL2_REG)); in da1469x_TSMC_pd_apply_preferred()
171 write32_mask(0x40000000, 0x40096255, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL3_REG)); in da1469x_TSMC_pd_apply_preferred()
173 write32_mask(0x000000ff, 0x00000180, REG_TO_PTR(CRG_XTAL->XTALRDY_CTRL_REG)); in da1469x_TSMC_pd_apply_preferred()
194 write32_mask(0x3ff00000, 0x000afd70, REG_TO_PTR(CRG_XTAL->CLK_FREQ_TRIM_REG)); in da1469x_GF_pd_apply_preferred()
195 write32_mask(0x000000c0, 0x00000562, REG_TO_PTR(CRG_XTAL->TRIM_CTRL_REG)); in da1469x_GF_pd_apply_preferred()
196 write32_mask(0x1fc38002, 0x0c01e6b6, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL0_REG)); in da1469x_GF_pd_apply_preferred()
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Dda1469x_clock.h177 return 0 != (CRG_XTAL->PLL_SYS_STATUS_REG & CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk); in da1469x_clock_is_pll_locked()
186 return ((CRG_XTAL->PLL_SYS_CTRL1_REG & IS_PLL_ENABLED_BITFIELDS) == IS_PLL_ENABLED_BITFIELDS); in da1469x_clock_sys_pll_is_enabled()
/hal_renesas-latest/smartbond/sdk/bsp/include/
DDA1469xAB.h1840 #define CRG_XTAL ((CRG_XTAL_Type*) CRG_XTAL_BASE) macro