Lines Matching refs:CRG_XTAL

166 		write32_mask(0x3ff00000, 0x000afd70, REG_TO_PTR(CRG_XTAL->CLK_FREQ_TRIM_REG));  in da1469x_TSMC_pd_apply_preferred()
167 		write32_mask(0x000000c0, 0x00000562, REG_TO_PTR(CRG_XTAL->TRIM_CTRL_REG));  in da1469x_TSMC_pd_apply_preferred()
168 		write32_mask(0x03c38002, 0x0801e6b6, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL0_REG));   in da1469x_TSMC_pd_apply_preferred()
169 		write32_mask(0x007fff00, 0x7500a1a4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL1_REG));  in da1469x_TSMC_pd_apply_preferred()
170 		write32_mask(0x00000fff, 0x001e45c4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL2_REG));  in da1469x_TSMC_pd_apply_preferred()
171 		write32_mask(0x40000000, 0x40096255, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL3_REG));  in da1469x_TSMC_pd_apply_preferred()
173 		write32_mask(0x000000ff, 0x00000180, REG_TO_PTR(CRG_XTAL->XTALRDY_CTRL_REG));  in da1469x_TSMC_pd_apply_preferred()
194 		write32_mask(0x3ff00000, 0x000afd70, REG_TO_PTR(CRG_XTAL->CLK_FREQ_TRIM_REG));  in da1469x_GF_pd_apply_preferred()
195 		write32_mask(0x000000c0, 0x00000562, REG_TO_PTR(CRG_XTAL->TRIM_CTRL_REG));  in da1469x_GF_pd_apply_preferred()
196 		write32_mask(0x1fc38002, 0x0c01e6b6, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL0_REG));   in da1469x_GF_pd_apply_preferred()
197 		write32_mask(0x707fff00, 0x0500a1a4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL1_REG));  in da1469x_GF_pd_apply_preferred()
198 		write32_mask(0x00000fff, 0x001e45c4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL2_REG));  in da1469x_GF_pd_apply_preferred()
199 		write32_mask(0x40000000, 0x40096255, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL3_REG));  in da1469x_GF_pd_apply_preferred()
201 		write32_mask(0x000000ff, 0x00000180, REG_TO_PTR(CRG_XTAL->XTALRDY_CTRL_REG));  in da1469x_GF_pd_apply_preferred()