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Searched refs:CGC_MOMCR_RESERVED_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/ra8t1/
Dbsp_feature.h20 #define CGC_MOMCR_RESERVED_MASK (0x8U) /* RA8 has reserved bit in MOMCR that must be 1. */ macro
22 #define CGC_MAINCLOCK_DRIVE (0x05U | CGC_MOMCR_RESERVED_MASK)
24 #define CGC_MAINCLOCK_DRIVE (0x03U | CGC_MOMCR_RESERVED_MASK)
26 #define CGC_MAINCLOCK_DRIVE (0x00U | CGC_MOMCR_RESERVED_MASK)
/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/ra8d1/
Dbsp_feature.h20 #define CGC_MOMCR_RESERVED_MASK (0x8U) /* RA8 has reserved bit in MOMCR that must be 1. */ macro
22 #define CGC_MAINCLOCK_DRIVE (0x05U | CGC_MOMCR_RESERVED_MASK)
24 #define CGC_MAINCLOCK_DRIVE (0x03U | CGC_MOMCR_RESERVED_MASK)
26 #define CGC_MAINCLOCK_DRIVE (0x00U | CGC_MOMCR_RESERVED_MASK)
/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/ra8m1/
Dbsp_feature.h20 #define CGC_MOMCR_RESERVED_MASK (0x8U) /* RA8 has reserved bit in MOMCR that must be 1. */ macro
22 #define CGC_MAINCLOCK_DRIVE (0x05U | CGC_MOMCR_RESERVED_MASK)
24 #define CGC_MAINCLOCK_DRIVE (0x03U | CGC_MOMCR_RESERVED_MASK)
26 #define CGC_MAINCLOCK_DRIVE (0x00U | CGC_MOMCR_RESERVED_MASK)