Searched refs:BSP_IRQ_GPT_COMBINED_EVENT_MASK (Results 1 – 1 of 1) sorted by relevance
35 #define BSP_IRQ_GPT_COMBINED_EVENT_MASK (0x1U) // Bit mas… macro544 R_ICU_NS->NS_GPT_INTMSK[reg_num] |= BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num; in R_BSP_IrqGptCombinedMaskSet()548 R_ICU_S->S_GPT_INTMSK[reg_num] |= BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num; in R_BSP_IrqGptCombinedMaskSet()566 R_ICU_NS->NS_GPT_INTMSK[reg_num] &= ~(BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num); in R_BSP_IrqGptCombinedMaskClear()570 R_ICU_S->S_GPT_INTMSK[reg_num] &= ~(BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num); in R_BSP_IrqGptCombinedMaskClear()617 R_ICU_NS->NS_GPT_INTCLR[reg_num] |= (BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num); in R_BSP_IrqGptCombinedStatusClear()621 R_ICU_S->S_GPT_INTCLR[reg_num] |= (BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num); in R_BSP_IrqGptCombinedStatusClear()
