Searched refs:BSP_CFG_SPI0ASYNCCLK (Results 1 – 2 of 2) sorted by relevance
40 #define BSP_CFG_SPI0ASYNCCLK (BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI0ASYNCCLK: 96… macro
32 #define BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS ((BSP_CFG_SPI0ASYNCCLK & 1U) << 24U)75 #define BSP_PRV_STARTUP_SCKCR3_SPI0ASYNCSEL_BITS (BSP_CFG_SPI0ASYNCCLK & 3U)
