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Searched refs:BSP_CFG_SCI5ASYNCCLK (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzn2l/
Dbsp_clock_cfg.h39 #define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96… macro
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c60 #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U)
70 #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 3U) << 18U)