Searched refs:BSP_CFG_SCI4ASYNCCLK (Results 1 – 2 of 2) sorted by relevance
38 #define BSP_CFG_SCI4ASYNCCLK (BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI4ASYNCCLK: 96… macro
39 #define BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS ((BSP_CFG_SCI4ASYNCCLK & 1U) << 31U)82 #define BSP_PRV_STARTUP_SCKCR3_SCI4ASYNCSEL_BITS ((BSP_CFG_SCI4ASYNCCLK & 3U) << 14U)
