Searched refs:BSP_CFG_SCI3ASYNCCLK (Results 1 – 2 of 2) sorted by relevance
37 #define BSP_CFG_SCI3ASYNCCLK (BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI3ASYNCCLK: 96… macro
38 #define BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS ((BSP_CFG_SCI3ASYNCCLK & 1U) << 30U)81 #define BSP_PRV_STARTUP_SCKCR3_SCI3ASYNCSEL_BITS ((BSP_CFG_SCI3ASYNCCLK & 3U) << 12U)
