Searched refs:BSP_CFG_SCI2ASYNCCLK (Results 1 – 2 of 2) sorted by relevance
36 #define BSP_CFG_SCI2ASYNCCLK (BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI2ASYNCCLK: 96… macro
37 #define BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS ((BSP_CFG_SCI2ASYNCCLK & 1U) << 29U)80 #define BSP_PRV_STARTUP_SCKCR3_SCI2ASYNCSEL_BITS ((BSP_CFG_SCI2ASYNCCLK & 3U) << 10U)
