Searched refs:BSP_CFG_SCI0ASYNCCLK (Results 1 – 2 of 2) sorted by relevance
34 #define BSP_CFG_SCI0ASYNCCLK (BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI0ASYNCCLK: 96… macro
35 #define BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS ((BSP_CFG_SCI0ASYNCCLK & 1U) << 27U)78 #define BSP_PRV_STARTUP_SCKCR3_SCI0ASYNCSEL_BITS ((BSP_CFG_SCI0ASYNCCLK & 3U) << 6U)
