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Searched refs:BSP_CFG_PLL1 (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzn2l/
Dbsp_clock_cfg.h13 #define BSP_CFG_PLL1 (BSP_CLOCKS_PLL1_INITIAL) /* PLL1 is initial state */ macro
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c516 #if (BSP_CLOCKS_PLL1_INITIAL != BSP_CFG_PLL1) in bsp_clock_init()
519 R_SYSC_S->PLL1EN = BSP_CFG_PLL1; in bsp_clock_init()