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Searched refs:BSP_CFG_FSELXSPI0_DIVSELXSPI0 (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzn2l/
Dbsp_clock_cfg.h45 #define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK0 12.5MHz */ macro
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c26 #define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U)
41 #define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U)