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Searched refs:BSP_CFG_DIVSELSUB (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzn2l/
Dbsp_clock_cfg.h31 #define BSP_CFG_DIVSELSUB (BSP_CLOCKS_DIVSELSUB_0) /* ICLK 200MHz */ macro
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_clocks.c58 #define BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS ((BSP_CFG_DIVSELSUB & 1U) << 5U)