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Searched refs:XRDC_HWCFG0_NMSTR_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_xrdc.c116 … config->masterNumber = ((base->HWCFG0 & XRDC_HWCFG0_NMSTR_MASK) >> XRDC_HWCFG0_NMSTR_SHIFT) + 1U; in XRDC_GetHardwareConfig()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h23341 #define XRDC_HWCFG0_NMSTR_MASK (0xFF00U) macro
23343 … (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK)
DRV32M1_zero_riscy.h30873 #define XRDC_HWCFG0_NMSTR_MASK (0xFF00U) macro
30875 … (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK)