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Searched refs:SYSTICK_LPIT (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c462 #define SYSTICK_LPIT LPIT1 macro
473 SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
474 SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
477 SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
480 SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1;
483 SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
492 SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
503 SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
Dsystem_RV32M1_ri5cy.c459 #define SYSTICK_LPIT LPIT0 macro
470 SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
471 SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
474 SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
477 SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1;
480 SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
489 SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
500 SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);