Home
last modified time | relevance | path

Searched refs:SIRCCFG (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c44 #define SCG_SIRCCFG_RANGE_VAL ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT)
447 SCG->SIRCCFG = SCG_SIRCCFG_RANGE(config->range); in CLOCK_InitSirc()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c404 …SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 20… in SystemCoreClockUpdate()
Dsystem_RV32M1_ri5cy.c401 …SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 20… in SystemCoreClockUpdate()
DRV32M1_ri5cy.h16192 …__IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x2… member
DRV32M1_zero_riscy.h17020 …__IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x2… member