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Searched refs:SCG_LPFLLCFG_FSEL_MASK (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c412 …SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 2… in SystemCoreClockUpdate()
Dsystem_RV32M1_ri5cy.c409 …SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 2… in SystemCoreClockUpdate()
DRV32M1_ri5cy.h17221 #define SCG_LPFLLCFG_FSEL_MASK (0x3U) macro
17229 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK)
DRV32M1_zero_riscy.h18049 #define SCG_LPFLLCFG_FSEL_MASK (0x3U) macro
18057 … (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK)
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c47 #define SCG_LPFLLCFG_FSEL_VAL ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT)